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IC Applications at CPPM since 5 years Rad-Hard and Pixels oriented

Over the past five years, the microelectronic team at CPPM has excelled in designing rad-hard and pixel-oriented integrated circuits (ICs). This includes developing low-voltage, low-noise analogue front-ends and classical digital designs, utilizing 8µm and 35µm CMOS technologies. Key projects include X-ray photon counting chips and a retina-inspired photodetection ASIC, showcasing bump bonding technology and sophisticated pixel architectures. Our extensive capabilities also encompass design and testing software using Cadence platforms, and PCB design with Cadence Allegro.

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IC Applications at CPPM since 5 years Rad-Hard and Pixels oriented

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  1. IC Applicationsat CPPMsince 5 yearsRad-Hard and Pixels oriented

  2. Microelectronic Team: 3 IC designers Low voltage, low noise Analogue front-ends Classical Building Block Digital design Test and Integration 6" probe station Wire bonding station Capability

  3. Design in .8µm CMOS • First Versions of a X-Ray photon counting chip • Pixels architecture from HEP design • (330µm by 330 µm) and 24x25 matrix • Bump bonding technology • Si sensor The chip XPAD1&2 with is sensor form the PIXSCAN. • 2 Full custom ASIC’s Analog front endComparator + Counter Control logic.

  4. Design in .35µ CMOS • Two Versions of a X-Ray photon integration chip • Matrix of 32 by 32 and 200 by 200 (pixel size 75µm square) • 2 Full custom ASIC’s Analog front endI/O Control logic.

  5. Design in .35µ CMOS • One version of a retina's fly • Matrix of 5 by 5 photodiode (300µm square) • Photodetection application • From 1 to 105 lux • Full custom ASIC Analog front end Low frequency FilterI/O ADC Control logic.

  6. Design in .25µm CMOS • Last Versions of a X-Ray photon counting chip • Pixels architecture from HEP design • (130µm by 130µm) and 80x120 matrix • Bump bonding technology • Si and CdTe sensor The chip XPAD3 with is sensor form the XPIX. • A full CPPM project Design, test and Integration

  7. Software IC design : Cadence platform • Cadence ( + Assura, Calibre, Hercules ) • HSpice, Eldo, UltraSim, SOC Encounter, Synopsys. PCB design: • Cadence Allegro design flow. Test and Automation • Altera Quartus + Nios • LabWindows

  8. test setup. Probe station semi automatic Wire bonding station

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