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DIGITAL SYSTEMS

DIGITAL SYSTEMS. Read Only– and Random Access Memory ( ROM – RAM) 2.12.04 Rudolf Tracht and A.J. Han Vinck. content. Read Only Memory Structure Random Access Memory SRAM DRAM. Read Only Memory (ROM). Storage of bits in a structured way: Two dimensional 2 n x b

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DIGITAL SYSTEMS

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  1. DIGITAL SYSTEMS Read Only– and Random Access Memory ( ROM – RAM) 2.12.04 Rudolf Tracht and A.J. Han Vinck

  2. content • Read Only Memory • Structure • Random Access Memory • SRAM • DRAM

  3. Read Only Memory (ROM) • Storage of bits in a structured way: • Two dimensional 2n x b • Every address specifies a pre-programmed output 2n addresses b-bits wide output

  4. Content „non-volatile“ • Non-volatile: Content stays on chip, even without power • Several types: • mask ROMs content programmed by manufacturer • PROM: Programmable ROM. All bits are pre-programmed to be 1. Bits (specified by address location) can be set to be equal to 0 by customer • EPROM „erasable PROM“:Ultraviolet light „resets“ all bits equal to 1 • EEPROM"electrically erasable PROM“: individual bits can be reset to 1. (application smart-cards)

  5. Some ROM applications • CPU primitive instruction set • CD-ROM • ROMfor logic functions, it stores a truth table • Structured design methods: simplification is not needed • Standardized building block: all ROMs are manufactured in identical steps except for the final customization phase • Example: Simple pre-programmed multiplier

  6. example • Multiply 2 x 2 bit words: A*B = C A*B = C 00 00 0000 10 00 0000 00 01 0000 10 01 0010 00 10 0000 10 10 0100 00 11 0000 10 11 0110 01 00 0000 11 00 0000 01 01 0001 11 01 0011 01 10 0010 11 10 0110 01 11 0011 11 11 1001

  7. 2n × b ROM organization • n address inputs specify 2n unique data words ROM-array decoder b - outputs

  8. Implementation with MOS i To store a 1 at a location: connect row j line to column i line with a MOSFET R L ••• L decoder H j j ••• To include a minterm to output: connect row j line to column i line with a transistor L L L H H invertor i H L L

  9. basic 2nx b ROM structures 2n-m x b bits wide address decoder select 1-out-of 2 m rows array m-bits 1 address select 1-out of 2n-m words multiplexer n-m-bits Chip select 1 CS OE 0 • output enable when • CS. NAND. OE = 0 1 ••• Output enable b bits

  10. Column multiplex four 8 x 1 multiplexer

  11. Cascading memory modules • example 256 X 8 ROM using 256 X 4 parts:

  12. example • Combinational logic implementation (two-level canonical form) using a ROM F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C' A B C F0 F1 F2 F3 8 x 4

  13. RAM- write or read information b-bits wide input ••• n-bits wide address 2n x b RAM b-bits wide output ••• ••• CS: Chip select OE: Output enable WE: Write enable CS OE WE control

  14. Content „Volatile“ • Volatile: looses content after Power-loss • Random Access Memory (RAM): access time constant • DRAM "dynamic" (high density, low speed) • used in main memory • SRAM "static" (low density, high speed) • used in CPU register file

  15. 2D Memory Architecture 2k-j bit line word line Aj Aj+1 Row Address storage (RAM) cell Row Decoder Ak-1 m2j Column Address A0 selects appropriate word from memory row A1 Column Decoder Aj-1 Read/Write Circuits Input/Output (m bits)

  16. Typical parallel DRAM organization 512 columns ••• 256Kb 512 rows 256Kb 256Kb 7 ••• 1 0 2Mbit DRAM: 256K x 8bits = 218 x 8bits = 29 rows x 29 columns x 8 bits

  17. AS7C4096

  18. Internal structure of a 1x2 static RAM in1 in0 in in out sel wr in out sel wr D Q C sel wr 1 x 2 decoder WE CS OE 1 1 0 latch open 0 1 0 latch closed 0 1 1 read content sel = 1 makes output available in out sel wr in out sel wr WE CS OE 1 0 1 out1 out0

  19. Bidirectional bus structure in in out sel wr in out sel wr D Q C sel wr 1 x 2 decoder WE CS OE 1 1 0 latch open 0 1 0 latch closed 0 1 1 read content 1 1 1 latch closed * 0 * latch closed sel = 1 makes output available in out sel wr in out sel wr WE CS OE 1 0 1 in1 out1 out0 in0

  20. Static RAM (SRAM) Read: Make word line H sense value on bit lines Write: Make word line H put values to Bit and !Bit flip-flop stays in stable state when word line  L !Bit = NOT(Bit) 6 MOSFETS  low density  higher cost/bit, but fast

  21. Dynamic RAM (DRAM) Read: - make word line H, - sense voltage on bit line (destroys saved value, i.e. content must be written back) Write: - make word line H - put new value on bit line - make word line L ( freeze the capacitor load ) Refresh cycles are needed for the whole memory to restore the content! (do dummy read) Small cell high density lower speed more difficult to produce

  22. memory access speed • Hardware Registers (CPU) • Random Access:access time is the same for all locations • SRAM: Static Random Access Memory • Low density, high power, expensive, fast • Static: content will last “forever”(until no power) • DRAM: Dynamic Random Access Memory • High density, low power, cheap, slow • Dynamic: need to be “refreshed” regularly • “Not-so-random” Access Technology: • Access time varies from location to location and from time to time • Examples: Disk, CDROM, DRAM page-mode access • Sequential Access Technology: access time linear in location (e.g.,Tape) size

  23. DRAM over time DRAM Generation 1st Gen. Sample Memory Size Die Size (mm2) Memory Area (mm2) Memory Cell Area (µm2) ‘84 ‘87 ‘90 ‘93 ‘96 ‘99 1 Mb 4 Mb 16 Mb 64 Mb 256 Mb 1 Gb 55 85 130 200 300 450 30 47 72 110 165 250 28.84 11.1 4.26 1.64 0.61 0.23 (from Kazuhiro Sakashita, Mitsubishi)

  24. trends Capacity Speed (latency) Logic: 2x in 3 years 2x in 3 years DRAM: 4x in 3 years 2x in 10 years Disk: 4x in 3 years 2x in 10 years

  25. Processor-DRAM Memory Gap (speed) µProc 60%/yr. (2X/1.5yr) 1000 CPU 100 Processor-Memory Performance Gap:(grows 50% / year) Performance 10 DRAM 9%/yr. (2X/10 yrs) DRAM 1 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000

  26. Page Mode/EDO RAM • Normal RAM drives many bits (row) out of array, selects few to output. • Adding latch at row outputs allows us to save an entire row of the RAM • Later accesses to the RAM can eliminate the row access time, just need column access time • Most common in DRAM, page-mode SRAMs also exist

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