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Introduction to CMOS VLSI Design Introduction

Introduction to CMOS VLSI Design Introduction. Manoel E. de Lima David Harris - Harvey Mudd College. Introduction. Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): very many Complementary Metal Oxide Semiconductor Fast, cheap, low power transistors

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Introduction to CMOS VLSI Design Introduction

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  1. Introduction toCMOS VLSIDesignIntroduction Manoel E. de Lima David Harris - Harvey Mudd College

  2. Introduction • Integrated circuits: many transistors on one chip. • Very Large Scale Integration (VLSI): very many • Complementary Metal Oxide Semiconductor • Fast, cheap, low power transistors • Today: How to build your own simple CMOS chip • CMOS transistors • Building logic gates from transistors • Transistor layout and fabrication • Rest of the course: How to build a good CMOS chip 0: Introduction

  3. WHY VLSI DESIGN? Money, technology, civilization

  4. Annual Sales • 1018 transistors manufactured in 2003 • 100 million for every human on the planet

  5. Digression: Silicon Semiconductors • Modern electronic chips are built mostly on silicon substrates • Silicon is a Group IV semiconducting material • crystal lattice: covalent bonds hold each atom to four neighbors http://onlineheavytheory.net/silicon.html

  6. Silicon Lattice • Transistors are built on a silicon substrate • Silicon is a Group IV material • Forms crystal lattice with bonds to four neighbors 0: Introduction

  7. Dopants • Silicon is a semiconductor • Pure silicon has no free carriers and conducts poorly • Adding dopants increases the conductivity • Group V: extra electron (n-type) • Group III: missing electron, called hole (p-type) 0: Introduction

  8. p-n Junctions • A junction between p-type and n-type semiconductor forms a diode. • Current flows only in one direction 0: Introduction

  9. A Brief HistoryInvention of the Transistor • Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable • 1947: first point contact transistor (3 terminal devices) • Shockley, Bardeen and Brattain at Bell Labs

  10. A Brief History, contd.. • 1958: First integrated circuit • Flip-flop using two transistors • Built by Jack Kilby (Nobel Laureate) at Texas Instruments • Robert Noyce (Fairchild) is also considered as a co-inventor Kilby’s IC smithsonianchips.si.edu/ augarten/

  11. A Brief History, contd. • First Planer IC built in 1961 • 2003 • Intel Pentium 4 processor (55 million transistors) • 512 Mbit DRAM (> 0.5 billion transistors) • 53% compound annual growth rate over 45 years • No other technology has grown so fast so long • Driven by miniaturization of transistors • Smaller is cheaper, faster, lower in power! • Revolutionary effects on society

  12. MOS Integrated Circuits • 1970’s processes usually had only nMOS transistors Inexpensive, but consume power while idle • 1980s-present: CMOS processes for low idle power Intel 1101 256-bit SRAM Intel 4004 4-bit Proc

  13. Moore’s Law • 1965: Gordon Moore plotted transistor on each chip • Fit straight line on semilog scale • Transistor counts have doubled every 26 months Integration Levels SSI: 10 gates MSI: 1000 gates LSI: 10,000 gates VLSI: > 10k gates http://www.intel.com/technology/silicon/mooreslaw/

  14. Transistor Types • Bipolar transistors • npn or pnp silicon structure • Small current into very thin base layer controls large currents between emitter and collector • Base currents limit integration density • Metal Oxide Semiconductor Field Effect Transistors • nMOS and pMOS MOSFETS • Voltage applied to insulated gate controls current between source and drain • Low power allows very high integration • First patent in the ’20s in USA and Germany • Not widely used until the ’60s or ’70s

  15. nMOS Transistor • Four terminals: gate, source, drain, body • Gate – oxide – body stack looks like a capacitor • Gate and body are conductors • SiO2 (oxide) is a very good insulator • Called metal – oxide – semiconductor (MOS) capacitor • Even though gate is no longer made of metal 0: Introduction

  16. nMOS Operation • Body is commonly tied to ground (0 V) • When the gate is at a low voltage: • P-type body is at low voltage • Source-body and drain-body diodes are OFF • No current flows, transistor is OFF 0: Introduction

  17. nMOS Operation Cont. • When the gate is at a high voltage: • Positive charge on gate of MOS capacitor • Negative charge attracted to body • Inverts a channel under gate to n-type • Now current can flow through n-type silicon from source through channel to drain, transistor is ON 0: Introduction

  18. pMOS Transistor • Similar, but doping and voltages reversed • Body tied to high voltage (VDD) • Gate low: transistor ON • Gate high: transistor OFF • Bubble indicates inverted behavior 0: Introduction

  19. Power Supply Voltage • GND = 0 V • In 1980’s, VDD = 5V • VDD has decreased in modern processes • High VDD would damage modern tiny transistors • Lower VDD saves power • VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, … 0: Introduction

  20. Transistors as Switches • We can view MOS transistors as electrically controlled switches • Voltage at gate controls path from source to drain 0: Introduction

  21. Transistors Input 0 Output poor 0 Input 0 Output Good 0 Input 1 Output good 1 Input 1 Output poor 1 0: Introduction

  22. Input 0 Output poor 0 Input 0 Output Good 0 Input 1 Output good 1 Input 1 Output poor 1 0: Introduction

  23. CMOS Inverter 0: Introduction

  24. CMOS Inverter 0: Introduction

  25. CMOS Inverter 0: Introduction

  26. Vdd Q1 Id Cload Q2 Vin Vout Vss CMOS Inverter 1- Vin = Vdd Análise do circuito: Vdd=+5V Ids Roff Cálculo de Vout Vdd = Ids(Roff+Ron) => Vdd = Ids.Roff+Ids.Ron => Vdd = Ids.Roff+Vout => Vout = Vdd-Ids.Roff 0V Ron Vout Ron < 1 Kohms Roff 1010Kohms Ids é pequeno, mas Roff é bastante grande 0V

  27. CMOS Inverter • Note que Vh = 5V, VL = 0V, e que Ids = 0A. • Isto significa que não existe praticamente dissipação de potência.

  28. CMOS Inverter Iil Iol Vol(max) Vil(max) Ron  1 K Transistor conduz Tensão(V) Nível ´0´ Vil(max) Tempo (seg) Ron  1 K +5V +5V Transistor não conduz R In Out Vih=´1´ GND GND Capacitor carregado (´1´)

  29. Vdd Q1 Id Cload Q2 Vin Vout Vss Cálculo de Vout Vdd = Ids(Roff+Ron) => Vdd = Ids.Roff+Ids.Ron => Vdd = Vout+Ids.Ron => Vout = Vdd-Ids.Ron Vdd=5V CMOS Inverter 2- Vin = 0V Análise do circuito: Vdd=+5V Ids Ron Roff Vout Ron < 1 Kohms Roff 1010Kohms Ids é muito pequeno 0V

  30. CMOS Inverter • Note que Vh = 5V, VL = 0V, e que Ids = 0A. • Isto significa que não existe praticamente dissipação de potência.

  31. CMOS Inverter X Voh(min) Vih(min) Roff  1010 Transistor não conduz Tensão(V) Nível ´1´ Vih(min) Tempo (seg) Ron  1 K +5V +5V Transistor conduz R In Out Iih Ioh Vil=0 GND GND Capacitor

  32. CMOS NAND Gate 0: Introduction

  33. CMOS NAND Gate 0: Introduction

  34. CMOS NAND Gate 0: Introduction

  35. CMOS NAND Gate 0: Introduction

  36. CMOS NAND Gate 0: Introduction

  37. saída A 0 1 0 1 1 B 1 1 0 Lógica Combinacional • Porta NAND Vcc (‘1’) Porta NAND de n-entradas Vcc (A+B) Vcc P n P B C A saída Saída Saída A B C n Dual Lógico N A B (A B) N A B GND GND (‘0’) GND

  38. CMOS NOR Gate 0: Introduction

  39. Lógica Combinacional saída A 0 1 0 1 0 B 1 0 0 • Porta NOR Vcc (‘1’) Vcc P n A B C Vcc (A B) A B P Dual Lógico saída saída Saída N N A B n C B A GND (A+B) GND GND (‘0’)

  40. 3-input NAND Gate • Y pulls low if ALL inputs are 1 • Y pulls high if ANY input is 0 0: Introduction

  41. Summary • MOS Transistors are stack of gate, oxide, silicon • Can be viewed as electrically controlled switches • Build logic gates out of switches 0: Introduction

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