1 / 5

From Paintable Computing to Scale-free Architectures

From research at Intel Corporation, DARPA, and DTO emerges a revolutionary concept in computing - Paintable Computing to Scale-Free Architectures. This innovative approach introduces new reliability challenges, soft error management, and robustness in extreme device variations. With a focus on scalability and meshed architectures, it promises smoother performance scaling and efficient code execution across various platforms. Dive into the future of computing with this ground-breaking solution.

ori-moss
Télécharger la présentation

From Paintable Computing to Scale-free Architectures

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. From Paintable ComputingtoScale-free Architectures Bill Butera Digital Enterprise Group Intel Corporation

  2. Paint Research, DARPA, DTO first HW Concept SWProof-of-concept Simulation ‘COTS’ HW

  3. Wider Extreme device variations Soft Error FIT/Chip (Logic & Mem) Burn-in may phase out…? Time dependent device degradation Reliability – new challenges at extreme of device shrinkage Source: Shekhar Borkar- Intel CTG

  4. Scale-free Architectures • SW techniques for reliable computation on meshes of unreliable HW nodes • High value “statistical workloads” running reliably on meshes of unreliable cores (nodes) • HW meshes whose performance scale smoothly with size -- over multiple orders of magnitude(1K nodes upward) • “Write once”, scale-agnostic application code • Excessive defect tolerance, smooth response to soft error. • Shortened HW design cycle, minimum form factor, faster yield ramps. Farm (300K nodes) Server (50K) Desktop (20K) UMPC (2K) Cell phone (1K) All platforms with the same short design cycle

  5. David Dalrymple Ara Knaian

More Related