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From Paintable Computing to Scale-free Architectures

From Paintable Computing to Scale-free Architectures. Bill Butera Digital Enterprise Group Intel Corporation. Paint Research, DARPA, DTO first HW. Concept. SW Proof-of- concept. Simulation. ‘COTS’ HW. Wider. Extreme device variations. Soft Error FIT/Chip (Logic & Mem).

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From Paintable Computing to Scale-free Architectures

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  1. From Paintable ComputingtoScale-free Architectures Bill Butera Digital Enterprise Group Intel Corporation

  2. Paint Research, DARPA, DTO first HW Concept SWProof-of-concept Simulation ‘COTS’ HW

  3. Wider Extreme device variations Soft Error FIT/Chip (Logic & Mem) Burn-in may phase out…? Time dependent device degradation Reliability – new challenges at extreme of device shrinkage Source: Shekhar Borkar- Intel CTG

  4. Scale-free Architectures • SW techniques for reliable computation on meshes of unreliable HW nodes • High value “statistical workloads” running reliably on meshes of unreliable cores (nodes) • HW meshes whose performance scale smoothly with size -- over multiple orders of magnitude(1K nodes upward) • “Write once”, scale-agnostic application code • Excessive defect tolerance, smooth response to soft error. • Shortened HW design cycle, minimum form factor, faster yield ramps. Farm (300K nodes) Server (50K) Desktop (20K) UMPC (2K) Cell phone (1K) All platforms with the same short design cycle

  5. David Dalrymple Ara Knaian

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