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LAB 7: WDT+ and Low-Power Optimization

CS 4101 Introduction to Embedded Systems. LAB 7: WDT+ and Low-Power Optimization. Chung-Ta King National Tsing Hua University. Introduction. In this lab, we will learn WDT+ as the interval timer Configuring the low-power mode of MSP430 . WatchDog Timer +. WDT+.

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LAB 7: WDT+ and Low-Power Optimization

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  1. CS 4101 Introduction to Embedded Systems LAB 7: WDT+ and Low-Power Optimization Chung-Ta King National Tsing Hua University

  2. Introduction • In this lab, we will learn • WDT+ as the interval timer • Configuring the low-power mode of MSP430

  3. WatchDog Timer +

  4. WDT+ • Watchdog timer+ (WDT+) is a 16-bit timer that can be used as a watchdog or interval timer • Watchdog timer: • Performs a system restart after a software problem occurs, e.g., unintended infinite loop • Counts up and resets system when it reaches limit • The program must keep clearing the counter before the limit is reached to prevent a reset

  5. Control of WDT+ • Control register: WDTCTL • Password protected: to guard against accidental writes by requiring writing password WDTPW = 0x5A in upper byte  reset if password incorrect • But, reading WDTCTL returns 0x69 in upper byte • The lower byte of WDTCTL contains the bits that control the operation of the watchdog timer

  6. WDT+ as Interval Timer • Set WDTTMSEL bit in WDTCTL to 1 • Set WDTSSEL bit in WDTCTL to select clock source: SMCLK or ACLK • Default clock is SMCLK derived from DCO at 1 MHz default period is 32768 counts, or about 32 ms • Set WDTISx bits in WDTCTL to select interval • Clock source divided by 64, 512, 8192, or 32,768 • Set WDTCNTCL bit in WDTCTL to clear counter

  7. WDT+ Control Register

  8. WDT+ Interrupt • WDT+ uses two bits in the Special Function Registers (SFRs) for interrupt control • WDT+ interrupt flag, WDTIFG, located in IFG1.0 • WDT+ interrupt enable, WDTIE, located in IE1.0 • WDTIFG is set when time interval expired • WDTIFG will request an interrupt if • WDTIE in IE1.0 and GIE in SR are enabled • WDTIFG can be automatically set/reset

  9. Sample Code (MSP430G2xx1 _wdt_01) • Toggle P1.0 using interval from WDT+ at about 32ms based on default DCO/SMCLK

  10. Low-Power Optimization

  11. Low-Power Mode

  12. Power Saving in MSP430 • The most important factor for reducing power consumption is using the MSP430 clock system to maximize the time in LPM3 “Instant on” clock

  13. Sample Code (MSP430G2xx1 _ta_01) • Toggle P1.0 using TA_0 every 50000 cycles Use _BIC_SR_IRQ(LPM0_bits) to exit LPM0

  14. Basic Lab (This lab is an extension from Lab 4) • Flash green LED at 1 Hz using interrupt from Timer_A, driven by SMCLK sourced by VLO. While green LED flashing at 1 Hz, pushing the button flashes red LED at 2Hz and releasing the button turns off red LED. Use low-power mode as much as possible. • Hint: PORT1_VECTOR as interrupt type, WDT+ to control the flashing of red LED • Hint: Use P1IES to change the trigger mode (“High to Low” or “Low to High”)

  15. P1IES Timer_A, driven by SMCLK sourced by VLO. BCSCTL3

  16. Bonus Flash green LED at 1 Hz using interrupt from Timer_A, driven by ACLK sourced by VLO in LPM3. While pushing the button, change from LPM3 to LPM0, stop flashing green LED, and flash red LED at 2 Hz using interrupt from Timer_A, driven by SMCLK sourced by VLO. Releasing the button returns the system to LPM3 and stops red LED flashing.

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