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Lab6 On-Chip Bus

Lab6 On-Chip Bus. Speaker: Yu-Lin Hsiao Advisor: Prof. Chun-Yao Wang August 17, 2005. Department of Computer Science National Tsing Hua University. Outline. Overview of the AMBA specification Advanced High-performance Bus (AHB) Advanced Peripheral Bus (APB)

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Lab6 On-Chip Bus

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  1. Lab6 On-Chip Bus Speaker: Yu-Lin Hsiao Advisor: Prof. Chun-Yao Wang August 17, 2005 Department of Computer Science National Tsing Hua University

  2. Outline • Overview of the AMBA specification • Advanced High-performance Bus (AHB) • Advanced Peripheral Bus (APB) • Lab6-Exp：On-Chip Bus

  3. AMBA • Advanced Microcontroller Bus Architecture • Standardize the on-chip connection of different IPs • AMBA spec. defines three different buses： • ASB (Advanced System Bus) • AHB (Advanced High-performance Bus) • APB (Advanced Peripheral Bus)

  4. AMBA Architecture

  5. Outline • Overview of the AMBA specification • Advanced High-performance Bus (AHB) • Advanced Peripheral Bus (APB) • Lab6-Exp：On-Chip Bus

  6. initiate read/write operation by providing an address and control information respond to read/write operation within a given address-space range ensure transfer operation is mutual exclusive decode the address of transfer to select a specific slave AHB Interconnection

  7. Overview of AHB Operation (1/2) • Master asserts a request signal to the arbiter. • Arbiter uses arbiter grant signals indicate which the master will be granted use of the bus. • A granted bus master starts an AMBA AHB transfer by driving the address and control signals. • The slave shows the status using the response signals. grant Arbiter request Master Slave address and control response

  8. Overview of AHB Operation (2/2) • Two different forms of burst transfer are allowed： • incrementing bursts, which do not wrap at address boundaries • wrapping bursts, which wrap at particular address boundaries. • Transfer types：( HTRANS[1:0] ) • IDLE：no data transfer is required • BUSY：continue with a burst of transfers, but next transfer can not take place immediately • NONSEQ：the first transfer of a burst or a single transfer • SEQ：the remaining transfers in a burst are SEQUENTIAL and the address is related to the previous transfer.

  9. Basic Transfer • An AHB transfer consists of two distinct sections： • The address phase, which lasts only a single cycle. • The data phase, which may require several cycles.

  10. Master Interface

  11. Burst Signal Encoding

  12. Four-beat Incrementing Burst

  13. Four-beat Wrapping Burst wrapping (0x40 mod 0x10 = 0; 0x40-0x10=0x30)

  14. Slave Interface

  15. Split Transfers • Improve the overall utilization of the bus by splitting the operation of the master providing the address to a slave from the operation of the slave responding with the appropriate data. • When a transfer occurs, the slave can decide to issue a SPLIT response if it believes the transfer will take a large number of cycles to perform.

  16. HGRANT2 = 1 HSPLITx HGRANT1 = 1 data data address address Split Transfer Sequence Arbiter Slave1 SPLIT SPLIT SPLIT Master1 Master2 Slave2

  17. Arbiter Interface

  18. Decoder Interface

  19. Outline • Overview of the AMBA specification • Advanced High-performance Bus (AHB) • Advanced Peripheral Bus (APB) • Lab6-Exp：On-Chip Bus

  20. APB Components • APB master： • the APB bridge is the only bus master on the AMBA APB. • APB slaves

  21. PSEL1 PSEL2 Address & PWDATA PSEL4 PSEL3 PRDATA APB Architecture Address & PWDATA PSEL PRDATA Slave1 Slave2 APB Bridge AHB /ASB slave interface Slave3 Slave4

  22. APB State Diagram

  23. Write Transfer from AHB IDLE SETUP ENABLE IDLE

  24. Read Transfer to AHB IDLE SETUP ENABLE IDLE

  25. Outline • Overview of the AMBA specification • Advanced High-performance Bus (AHB) • Advanced Peripheral Bus (APB) • Lab6-Exp：On-Chip Bus

  26. Goal To introduce the interface design conceptually. Study the communication between FPGA on logic module and ARM processor on core module. We will introduce the AMBA in detail Principle Overview of the AMBA specification Introducing the AMBA AHB AMBA AHB signal list The ARM-based system overview Guide We use a simple program to lead student understanding the AMBA Requirements and Exercises To trace the hardware code and software code, indicate that software how to communicate with hardware using the AMBA interface Discussion If we want to design an accumulator (1,2,3…) , how could you do to implement it using the scratch code? If we want to design a hardware using FPGA, how could you do to add your code to the scratch code and debugger it ? To study the ARMB bus standard, try to design a simple AMBA interface Lab 6: On-Chip Bus

  27. References [1] AMBA20.pdf [2] DUI0098B_AP_UG.pdf [3] DUI146B_LM600_UG.pdf [4] CIC News Issue 10

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