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Aerospace Corp. Experiments

Aerospace Corp. Experiments. Aerospace Corp. Experiments. A series of 11 experiments Description Objective Status Schedule. The Experiments. Step/Stress Test – Voltage Test Contractor Reliability Model Validation Aerospace Review Wafer Fab Data Aerospace

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Aerospace Corp. Experiments

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  1. Aerospace Corp. Experiments

  2. Aerospace Corp. Experiments • A series of 11 experiments • Description • Objective • Status • Schedule

  3. The Experiments • Step/Stress Test – Voltage Test Contractor • Reliability Model Validation Aerospace • Review Wafer Fab Data Aerospace • Noise Susceptibility Tests Actel • Antifuse DPA/FA Aerospace • Programming Hardware Review Aerospace • Failure rate Measurement Actel • Effects of Programming Procedures Aerospace and Conditions on Antifues Rel. • Board Level I/O Noise Measurements Contractor • Screen Test Development Actel • Long-Term Validation/Space Qualification Actel

  4. Experiment 1 • Step Stress Test -- Voltage Stress • Description: • Voltage step stress tests are being performed. • Objective: • To determine core voltage levels that would result in overstressed programmed antifuses. • To explore the “tail of the distribution” of programmed antifuses and determine their behavior relative to overstress conditions

  5. Experiment 2 • Reliability Model Validation • Description: • Actel’s reliability model developed based on earlier technology (0.6 um). • Current model and data may be inadequate to qualify 0.25 um technology for space applications. • Objective: • Determine if data is sufficient to validate reliability predictions • Validate model and determine if additional antifuse test set measurements are required. • Update model for 0.25 um technology if necessary.

  6. Experiment 3 • Review Wafer Fabrication Data • Description: • Wafer fab process data related to antifuses might show variability and defect trends that could provide information for the root cause analysis. • Objective: • Review wafer fab process data (process monitor information) and wafer level reliability data to understand variability between wafers within a lot, lot to lot variability and any trends that could be detected within the antifuses.

  7. Experiment 4 • Noise Measurement • Description: • Noise on the core voltage lines or temporary undershoot on the I/O have been identified as potential sources of electrical overstress of programmed antifuses. • Simultaneous switching undershoot has been identified as a potential contributor to failure. • A series of tests to induce controlled levels of noise on the core power lines or levels of simultaneous switching undershoot will be tested. • Objective: Assess the impact of voltage noise and/or undershoots on part reliability.

  8. Experiment 5 • Antifuse DPA/FA • Description: • Root cause of antifuse failure has not been determined. • Actel claims that overstress is the major culprit. • DPA and FA is needed to determine the root cause of antifuse failures in order to design procedures for screening, life testing, and space qualifying Actel FPGA parts. • Objective: • To determine root cause of post-programming Actel FPGA antifuse failures.

  9. Experiment 6 • Programming Hardware Review • Description: • Potential for programming hardware to cause overstress of antifuses during programming • Objective: • Perform design review and testing of BP Microsystems programming hardware to ensure no potential for overstress during programming operation. • See if any compromises in hardware construction can contribute to damaged antifuses.

  10. Experiment 7 • Failure Rate Measurement • Description: • Failure rate of FPGA antifuses is not known. • Objective: • Develop a test to determine intrinsic die failure rates of programmed FPGA parts designated for space application. • Test to be performed on a specially programmed FPGA free of external voltage spikes.

  11. Experiment 8 • Effects of Programming Procedures and Conditions on Antifuse Reliability • Description: • There is limited information regarding multiple versus single pulse trains and their possible correlation to FPGA reliability • Objective: • Develop an experiment to characterize single versus multiple pulse cycling on reliability.

  12. Experiment 9 • Board-level I/O noise measurements • Description: • Signal reflections on lines have been identified as a potential cause of overstress due to the absence of terminations • Objective: • Verify appropriate board design and identify potential sources of overstress for corrective action. • Determine impact of terminations on line signal integrity. • Develop method of improved termination

  13. Experiment 10 • Screen Development • Description • Based on the failures observed of the FPGAs in contractor hardware, a root cause investigation was initiated. • Contractors would like to be able to use existing stock of FPGA devices and devices already installed on boards. • The contractors would like to have a screen test to provide them confidence that the devices will meet the reliability and mission requirements for their programs. • Objective: • Based on the results of the root cause investigation, develop a part level and/or box/system level screen that could be performed to provide assurances the FPGAs that successfully pass the screen are acceptable for flight utilization.

  14. Experiment 11 • Long Term Validation/Space Qualification • Description: • A review of the reliability and qualification data has shown some concerns. • A long term validation of the reliability and a formal space qualification of the product must be performed. • Objective: • The long term reliability validation including the performance of a formal space qualification must be initiated.

  15. Schedule

  16. 7/10 Down from 800 parts Main Test Sequence 504 hrs 168 hrs Expected start date ~ May 19 8/21 6/18 6/29 7 - Core switching only 4d - 7 + In spec I/O switching 4a = SSO 4b = SSU 4c = Vcca 8/25 Project 4a Project 4d Project 4b 600 parts Project 7 Project 4c Project 4 and 7 Flow • Notes: • Dates and Plans Subject To Change!! • 400 0.22 µm/UMC SX-A devices to follow.

  17. Colonel L.'s Early Stress Test phase 7 - Core switching only 4d - 7 + In spec I/O switching 4a = SSO 4b = SSU 4c = Vcca Project 4a 550 parts Project 7 Project 4b 168 hrs Project 4c Project 4 and 7 Flow Expected start date ~Apr 27 Completion dates not known at this time.

  18. Agreement Details • Boeing will buy 350 parts from Actel for use in testing • All 350 parts are burned in and available at Actel in a few weeks • 100 of the 350 parts are from mixed lots • Actel will proceed to burn in 200 of the 800 parts they’re supplying to the Tiger Team effort • Actel will use some of their production facility burn-in-boards to make those parts ready NLT 27 April • Different lot parts will be spread into both tiger-team and early stress test sequences • Want to ensure tests have samples from multiple lots • Aerospace will provide direction for tiger-team sequence activities • Boeing will provide direction for early stress test sequence activities • Aerospace/Tiger-team will have access to all data

  19. Agreement Details (continuation 1) • Tiger-team will work out details of testing levels and duration in the stressing part (“nominally” 4a/b/c) of the early stress test sequence • Tiger-team will be asked to consider elimination of Vcca test (Project 4c) in both the early stress test and tiger-team sequences • Actel experience and other tests indicate it may not be effective stressing • Will enhance statistics in the remaining tests

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