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Chapter Goals

Chapter Goals. Describe CPU instruction and execution cycles Explain how primitive CPS instructions are combined to form complex processing operations Describe key CPU design features, including instruction format, word size, and clock rate

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Chapter Goals

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  1. Chapter Goals • Describe CPU instruction and execution cycles • Explain how primitive CPS instructions are combined to form complex processing operations • Describe key CPU design features, including instruction format, word size, and clock rate • Describe the function of general-purpose and special-purpose registers Systems Architecture, Fifth Edition

  2. Chapter Goals (continued) • Compare and contrast CISC and RISC CPUs • Describe the principles and limitations of semiconductor-based microprocessors Systems Architecture, Fifth Edition

  3. Systems Architecture, Fifth Edition

  4. CPU Operation • General and Specific Purpose Processors. • Control unit • Moves data and instructions between main memory and registers • Arithmetic logic unit (ALU) • Performs computation and comparison operations • Set of registers • Storage locations that hold inputs and outputs for the ALU Systems Architecture, Fifth Edition

  5. Actions Performed by CPU Systems Architecture, Fifth Edition

  6. Systems Architecture, Fifth Edition

  7. Instructions and Instruction Sets • Instruction • Lowest-level command • In memory, it is a bit string, logically divided into components (op code and operands) • Three types of instructions (data movement, data transformation, sequence control) • Instruction sets • Collection of instructions that a CPU can process • They are vary among CPU in the following ways: • Number of instructions. • Size of individual instructions, op codes, and operands. • Supported data types. • Number and complexity of processor operations performed by individual instructions. Systems Architecture, Fifth Edition

  8. Systems Architecture, Fifth Edition

  9. Data Movement Instructions • A MOVE (copy) instruction copies data bits to storage locations (registers and primary storage locations). • A LOAD operation is a data transfer from main memory into a register. • A STORE operation is a data transfer from registers to main memory. • Copy data (MOVE) among registers, primary storage, secondary storage, and I/O devices Systems Architecture, Fifth Edition

  10. Data Transformations • The most primitive data transformation instructions are based on Boolean logic. • Implement simple Boolean operations (NOT, AND, OR, and XOR) • Implement addition (ADD) • Implement bit manipulation (SHIFT) • Logical shift • Arithmetic shift Systems Architecture, Fifth Edition

  11. NOT: • Converts 0 to 1 and vice versa. • NOT 0 = 1 and NOT 1 = 0. • NOT 10001011 = 01110100 • Note that NOT has only one data input, whereas all other Boolean instructions have two. Systems Architecture, Fifth Edition

  12. Systems Architecture, Fifth Edition

  13. AND: • The final answer of AND operations is true, if both operands are true. • Ex: 10001011 AND 11101100 = 10001000 • OR: • Two types: • Inclusive OR (inclusive generally is omitted): generates the value true if either on of the operands is true. ex: 10001011 OR 11101100 = 11101111. • Exclusive OR: generates true if either but not both operands are true. ex: 10001011 XOR 00001111 = 10000100. Systems Architecture, Fifth Edition

  14. Every bit in a bit string can be inverted by XORing with a string of ones. Ex. 10001011 XOR 11111111 = 01110100. • ADD: an ADD accepts two numeric inputs and produces their arithmetic sum. Ex: 10001011 ADD 00001111 = 10011010. • Note that the mechanics of the addition operation are the same regardless of what the bit strings represent. • If they represent unsigned binary numbers, then the operation is 139 + 15 = 154. • If they represent signed integers in Two’s Complement format : -117 + 15 = -102 Systems Architecture, Fifth Edition

  15. SHIFT: bit strings can be shifted to the right or to the left by number that could be greater than 1. • There are two types of SHIFT: • Logical (to check the sign). • Arithmetic (multiplication or division). Systems Architecture, Fifth Edition

  16. Systems Architecture, Fifth Edition

  17. Systems Architecture, Fifth Edition

  18. Systems Architecture, Fifth Edition

  19. Sequence Control Operations • Control the next instruction to be fetched or executed • Operations • Unconditional branch • Conditional branch • Halt Systems Architecture, Fifth Edition

  20. Complex Processing Operations • Implemented by appropriate sequences of primitive instructions, for example: converting subtraction to addition. • For example: the complement of 0011, represented as two’s comp. can be derived as: XOR(0011,1111) + 0001 = 1101 = -3. • Represent combinations of primitive processing operations • Represent a tradeoff between CPU complexity and • Programming simplicity • Program execution speed Systems Architecture, Fifth Edition

  21. For example: to calculate 7-3, we do the following:ADD(ADD(XOR(0011,1111),0001),0111) = ADD(ADD(1100,0001),0111) =ADD(1101,0111) = 10100 • Because we have here 4 bits only, then we delete the left most 1 to get 0100 = 4. • Comparison operations can be done the same way. • Comparison operations have a result of 0 to indicate false and anything else to indicate true. • To compute whether A==B or not, we derive the comp. of B then add it to A. Systems Architecture, Fifth Edition

  22. If the two numbers are equal then the result will be zeros. • To Check whether A<B or A>B, we check the left most bit of the result, if 0 then false and if 1 then true. • SHIFT can be used to extract the sign bit. • For example: the comparison: 0111<0011 can be evaluated as:SHIFT(ADD(0111,ADD(XOR(0011,1111),0001)),0011) =SHIFT(ADD(0111,ADD(1100,0001)),0011)=SHIFT(ADD(0111,1101),0011)=SHIFT(0100,0011)=0000 = FALSE. Systems Architecture, Fifth Edition

  23. Short Programming Example, written using High level programming language: • IF (Balance < 100) then Balance= Balance – 5Endif • Consider Balance = 64. Systems Architecture, Fifth Edition

  24. Systems Architecture, Fifth Edition

  25. Instruction Set Extensions • All of the complex functions are implemented by primitive instructions discussed earlier. • Complex instructions represent a tradeoff between processor complexity and programming simplicity. • Complex instructions also represent a tradeoff between CPU complexity and execution speed. • Additional instructions required when new data types are added, for example making computations for double precision numbers (Floats and Longs). • Some include instructions that combine data transformation with data movement Systems Architecture, Fifth Edition

  26. Instruction Format • Recall that an instruction consists of an op code (instruction number) and zero or more operands (representing data values or storage locations). • Instruction Format: is a template describing op code position and length, and position, type, and length of each operand • Vary among CPUs (op code size, meaning of specific op code values, data types used as operands, length and coding format of each type of operand) • Most CPUs support multiple instructional formats Systems Architecture, Fifth Edition

  27. Systems Architecture, Fifth Edition

  28. Most CPUs represent the op code as an unsigned binary number, which provides 256 possible instructions numbered from 0 to 255. • Each operand represented by 4 bits, identifying one of 16 possible registers. Systems Architecture, Fifth Edition

  29. Systems Architecture, Fifth Edition

  30. Instruction Length • Instructions format within a CPU can be fixed or variable in length. • Fixed length instructions simplify the instruction-fetching process within the control unit. • If the instruction is fixed then the amount by which the instruction pointer must be incremented after each fetch is constant. This increment is the length of instruction. Systems Architecture, Fifth Edition

  31. With the variable length instruction, the amount by which the instruction pointer is incremented after a fetch is the length of the most recently fetched instruction. • The CU must calculate the length of every instruction to know the address of the next one. • This method consumes mot CPU power. • The fixed way also may consume more memory if the instruction does not have operands or have one operand. Systems Architecture, Fifth Edition

  32. Instruction Length Systems Architecture, Fifth Edition

  33. Reduced Instruction Set Computing (RISC) • Uses fixed length instructions, short instruction length, large number of general-purpose registers • Generally avoids complex instructions, especially those that combine data movement and data transformation • Simpler but less efficient than CISC (Complex Instruction Set Computing) Systems Architecture, Fifth Edition

  34. Why we need to eliminate complex instructions? • While complex instruction take less CPU cycle than reduced ones, also the big numbers of complex instructions need more times to be executed. • It has two main problems: • It complicated the CU because there are more instructions to interpret and usually more instruction formats and data types to deal with, Large instruction sets go hand by hand with the variable instruction formats, these problems make it is complex for fetching processes. • Large instruction sets generate problem in processor size. Systems Architecture, Fifth Edition

  35. A problem in RISC CPUs is the program size, because reducing the instruction set will generate more simple instructions, which in turn needs more memory. But memory improvements cost less then CPU improvements. Systems Architecture, Fifth Edition

  36. Clock Rate: • The system clock is a digital circuit that generates timing pulses and transmits them to other devices within the computer over a separate line on the control bus. • This signal is the heartbeat of the computer. • All of the actions in the computer are timed according to this clock. • The frequency of this clock, typically expressed in millions of cycles per second (MHz) is the clock rate of the system. Systems Architecture, Fifth Edition

  37. Instructions and execution cycles usually represent some fraction of the clock rate. • The speed of a computer is measured in millions of instructions per second (MIPS). Systems Architecture, Fifth Edition

  38. Number of instructions and execution cycles potentially available in a fixed time interval • Typically measured in thousands of MHz(1000 MHz = 1 GHz) • Rate of actual or average instruction execution is measured in MIPS or MFLOPS (millions of floating point operations per second) • CPU cycle time – inverse of clock rate • Cycle Time = 1/Clock Rate, 1/5 GHz = 0.2 nanosecond. • Wait state Systems Architecture, Fifth Edition

  39. CPU Registers • Primary roles • Hold data for currently executing program that is needed quickly or frequently (general-purpose registers), they are as scratch-pad. • Store information about currently executing program and about status of CPU (special-purpose registers) for example the address of the next program instruction, error messages, and signals from external devices. Systems Architecture, Fifth Edition

  40. General-Purpose Registers • Hold intermediate results and frequently needed data items such as loop counters or array indices. • Used only by currently executing program • Implemented within the CPU; contents can be read or written quickly. • Increasing their number usually decreases program execution time to a point (increase execution speed). • Storing data in memory (during the execution of a program) is slower than storing them in registers. • CPU contains dozens of registers. Systems Architecture, Fifth Edition

  41. Special-Purpose Registers • They are used by the CPU for specific purposes. • Track processor and program status • Types • Instruction register • Instruction pointer • Program status word (PSW) Systems Architecture, Fifth Edition

  42. When the CU fetches the instruction from memory, it stores it in the Instruction Register. • The CU then extracts the op code and operands from the instruction, this process is called Instruction Decoding. • The InstructionPointer is called ProgramCounter which used to store the address of the next instruction to be executed in the program. • The Instruction Pointer is incremented by the CU (static or dynamic value). • If there is a branch (unconditional and conditional), the value of the Instruction Pointer will be the Instruction that the CPU will move control to it. (Not the next instruction of the currently executed one). Systems Architecture, Fifth Edition

  43. The Program Status Word contains the status of the CPU and the status of the currently executed program. • Each bit contained in the PSW is a Boolean variable called flag, it represents one data item. • It has 3 primary uses: • Stores results of comparison operation • Controls conditional branch execution • Indicates actual or potential error conditions • 2 bits for comparison results ( we need 2 bits because we have 3 possible answers =, < , >). • Other bits are used for errors like: • Overflow, division by zero, …etc. Systems Architecture, Fifth Edition

  44. Word Size • A word is a unit of data that contains number of bits or bytes. • Number of bits a CPU can process at one time. • Word size is normally is the same as general-purpose register. • The CPU that can handle bigger word size is better than the one that handles smaller word size. (handling 64 bit in one instruction is better than handling 32 bit, the later needs two instructions). Systems Architecture, Fifth Edition

  45. Also busses wide must be with the same length of the word size.( wider is faster). • If the width is smaller, then they need to transfer data several times, not one time. • For example moving 64 bits as a whole, is faster than moving 16 bits 4 times. • Also memory is affected when dealing with 64 bits (for example) is better than less than that. • Maximizing the word size is not always a good solution, because when dealing with small numbers, the system will transfer zeros every time the system treat with the number. Systems Architecture, Fifth Edition

  46. Enhancing Processor Performance Systems Architecture, Fifth Edition

  47. Systems Architecture, Fifth Edition

  48. Range of Possible Approaches for Multiprocessing • Duplicate circuitry for some or all processing stages within a single CPU • Duplicate CPUs implemented as separate microprocessors sharing main memory and a single system bus • Duplicate CPUs on a single microprocessor that also contains main memory caches and a special bus to interconnect the CPUs Systems Architecture, Fifth Edition

  49. The Physical CPU • Electronic switches are the basic building blocks of the electronic circuits inside the CPU, they control the electrical current inside the CPU using transistors. • A Gate is a circuit that can perform a processing function on an individual binary digit. • Electrical device implemented as silicon-based microprocessor • Contains millions of switches, which perform basic processing functions Systems Architecture, Fifth Edition

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