Synthesizable VHDL LC-2 Created By: Eric Frohnhoefer & Ron Feliciano Under the Direction of:

1. Introduction Synthesizable VHDL LC-2 Created By: Eric Frohnhoefer & Ron Feliciano Under the Direction of: Professor Frank Vahid

2. Introduction Synthesizable LC-2 Model • Introduction into VHDL (5 min) • LC-2 overview (5 min) • Demonstration of fetch cycle (15 min) • Researching (5 min) • Question and Answer (remaining time)

3. Introduction into VHDL What is VHDL?? VHDL = (Very High Speed Integrated Circuit) Hardware Description Language What do we use VHDL for?? VHDL is a programming language used for verification and synthesis of digital designs. Features of VHDL • High level language • Allows for rapid development of digital designs • Syntactically similar to C++ • Various methods of hardware description • High level system verification

4. Introduction into VHDL VHDL code C++ code if ( condition ) then expression; end if; if ( condition ){ expression; } case ( variable ) is when condition => Expression; end case; switch ( variable ) { case condition : expression; break; } Operators = comparison := assignment <= assignment /= not equal Operators = assignment == comparison != not equal

5. Standard VHDL Libraries Overall structure of component (input and outputs) Start of behavioral code Code that describes actual process Introduction into VHDL LC-2 ALU VHDL Code library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; --LC-2 ALU--------------------------------------- entity LC2_ALU is port( A: in std_logic_vector (15 downto 0); B: in std_logic_vector (15 downto 0); S: in std_logic_vector (1 downto 0); O: out std_logic_vector (15 downto 0)); end LC2_ALU; architecture bhv of LC2_ALU is begin process(A, B, S) begin case S is when "00" => O <= A+B; when "01" => O <= A and B; when "10" => O <= A; when "11" => O <= not A; when others => null; endcase; end process; end bhv;

6. DataIn (0-15) Tri-State buffer System Bus IN WriteEnable Data 3:3 Reg Bank ADDR (0-2) enable Data 2:2 Data 1:1 OUT Data 0:0 DataOut (0-15) enable A B ALU Sel OUT LC-2 Logic Components Basic Logic Components Register/Register Bank Arithmetic Logic Unit (ALU)

7. LC-2 Overview • Instruction Cycle • Fetch - Fetch next instruction from main memory as indicated by the Program Counter (PC) • Decode - Decodes the instruction returned by the fetch cycle. • Address Evaluation - Calculate address of data and load into Memory Address Register (MAR). • Operand Fetch - Load data into Memory Data Register (MDR). • Execute - Perform given operation. • Store Result - Store result into memory. • Addressing modes • Immediate Mode (LEA) - DR = PC[15:9] @ pgoffset9 • Direct Mode (LD) - DR = mem[PC[15:9] @ pgoffset9] • Indirect Mode (LDI) - DR = mem[mem[PC[15:9] @ pgoffset9]] • Base+Offset Mode (LDR) - DR = mem[BaseR + ZEXT(index6)]

8. LC-2 Fetch Cycle PC_Gate <= ‘1’ MAR_ld <= ‘1’

9. LC-2 Fetch Cycle cont’d PC_gate <= ‘0‘ MAR_ld <= ‘0’ Read_Write <= ‘1’ MIO_enable <= ‘1’

10. LC-2 Fetch Cycle cont’d MIO_enable <= ‘0’ MDR_ld <= ‘1‘

11. LC-2 Fetch Cycle cont’d MDR_ld <= ‘0’ MDR_gate <= ‘1’ IR_ld <= ‘1’ PC_mux <= "00" PC_ld <= ‘1’

12. LC-2 Fetch Cycle cont’d IR_ld <= ‘0’ PC_ld <= ‘0’ MDR_gate <= ‘0’

13. LC-2 Stats Here are some of the statistics we obtained by synthesizing the LC-2 model down to gate level, using the Synopsys Design Compiler with medium mapping effort. We left the ram_modules in behavioral level code since they would normally not be synthesized into logic but rather loaded into a memory. • www.cs.ucr.edu/~efrohnho • www.cs.ucr.edu/~rfelicia • http://www.cs.ucr.edu/~vahid/sproj/lc2/index.html Eric’s Webpage Ron’s Webpage LC-2 Webpage

14. Tips for finding interesting research opportunities: • Find something that interests you. • Take relevant course work. • Do well in your classes. • Get to know your professors. • Don’t be afraid to ask. What to expect: • Work hard. • Work independently or with a small group. • Not to be paid. Benefits of doing research: • Looks good on resume. • Give you a chance to explore your field. • Make you more competitive in the work force. Researching