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VHDL and Sequential circuit Synthesis

VHDL and Sequential circuit Synthesis

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VHDL and Sequential circuit Synthesis

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  1. VHDL and Sequential circuit Synthesis • VHDL constructs versus automatic synthesis • What is synthesis? • Building blocks • Issues and example • Tools and targets

  2. Hardware Description Language (HDL) • Describe hardware – not software • Description – structure • Language – strong syntax and type declarations • Start with a block diagram

  3. HDL Constructs & Key Ideas Entity Architecture Port Process Signal & types Variable Conditionals – if, case, next, while After, wait (until) Component & port map Generate, block Concurrency Sequential Sensitivity List Principles are the same for most HDL languages and all practically used languages

  4. Multiple Architectures for the same entity There are many ways to describe the same circuit Entity COMBO is port (A,B,C: in bit; D: out bit); End COMBO; architecture EG1 of COMBO is Begin D <= (A nand B) xor C; End EG1; Concurrent equations

  5. Multiple Architectures for the same entity Xor described behaviorally inside the process architecture EG2 of COMBO is Begin process (A, B, C) begin if (C = ‘0’) then D <= A nand B; else D<= A and B; end if; end process; end EG2; Entity COMBO is port (A,B,C: in bit; D: out bit); End COMBO;

  6. Multiple Architectures for the same entity Mix concurrent statements and processes architecture EG3 of COMBO is signal T : bit; begin T <= A nand B; p1 : process (T,C) begin D <= T xor C; end process p1; end EG3; Entity COMBO is port (A,B,C: in bit; D: out bit); End COMBO; As we see, even for a very small circuit there are several descriptions possible. In case of large sequential systems, this number is extremely large, how to select best? How to program in such a way that the system will generate the best?

  7. What is Synthesis? • Generate hardware from HDL • Eg. C <= A nand B gives • Is it that simple? • No, it is a very complex process in which time and space can be rearranged and trade-offs investigated, especially for sequential circuits. A C B

  8. What is Synthesis? We use Leonardo Spectrum software at PSU

  9. Watch out for these statements! • Time expressions – after • Assert, Text I/O • Configuration declarations • Dynamic Loops • Initial values • Sensitivity lists } } Simulation purpose Simulation purpose Affect synthesized structures }

  10. Basic Sequential elements • Latches • Cheaper than FFs • Troubles with timing analysis and synchronization • Possible implication of undesired latches when you assign improper modeling type • Flip-flops • Edge sensitive • Asynchronous and synchronous set and reset

  11. Descriptions 4s5ng 3atches • You have to distinguish between combinational, latches and synchronized Flip-Flops • Lack of understanding is a common source of errors. • We will first cover latches, • Next we will cover flip-flops

  12. Description with Latches • Data input: D; enable: LE; output: Q. signal D, LE, Q: bit ; ... b1 : process (D, LE) begin if (LE = ’1’) then Q <= D; end if ; end process ; b2 : block (LE=’1’) begin Q <= GUARDED D; end block ; These are two equivalent descriptions of latch Observe that these two syntax examples involve storing the signal in a memory

  13. Description using Latches These are two equivalent descriptions Example: library IEEE; use IEEE.std_logic_1164.all; entity LATCHES is port (D1, D2, LE: in std_logic; Q : out std_logic); end LATCHES; architecture EG of LATCHES is begin b1: block (LE = '1') begin Q <= guarded D1 xor D2; end block; end EG; library IEEE; use IEEE.std_logic_1164.all; entity LATCHES is port (D1, D2, LE: in std_logic; Q : out std_logic); end LATCHES; architecture EG of LATCHES is begin process (D1, D2, LE) begin if (LE = '1') then Q <= D1 xor D2; end if ; end process; end EG; This is “Logic Enable” NOT clock

  14. Modeling Latches when: Q <= D when En=‘1’ else Q; ... Q <= D when En=‘1’ elseunaffected;(VHDL 93) if controlled by Enable library IEEE; use IEEE.Std_Logic_1164.all; entity Latch is port (D, En : in Std_Logic; Q : out Std_Logic); end Latch; architecture RTL of Latch is begin L1: process(D, En) begin if En=‘1’ then Q <= D; endif; end process; end RTL;

  15. Description using Edge Triggered Flip Flops • Flip Flop is based on a clock signal. • Rising/Falling edge triggered. signal D, Q, clk : bit ; .... process (clk) begin if (clk’event and clk=’1’) then Q <= D; end if ; end process ; Rising edge

  16. Description using Edge Triggered Flip Flops with complex excitation function Example: library IEEE; use IEEE.std_logic_1164.all; entity FLIPFLOP is port (D1, D2, clk: in std_logic; Q : out std_logic); end FLIPFLOP; architecture EG of FLIPFLOP is begin process (clk) begin if (clk’event and clk='1') then Q <= D1 xor D2; end if ; end process; end EG;

  17. Descriptions of Synchronous Set/Reset Flip Flops • Data and reset is NOT on sensitivity list. signal D, Q, clk, reset : bit ; ... process (clk) begin if (clk’event and clk = ’1’) then if reset = ’1’ then D <= ’0’ ; else Q <= D ; end if ; end if ; end process ; D is symbol of next state, not current state

  18. Synchronous Set/Reset Flip Flops • No sensitivity list. signal D, Q, clk, reset : bit ; ... b3 : block (clk’event and clk=’1’) begin Q <= GUARDED ’0’ when reset = ’1’else D ; end block ; Role of GUARDED in synchronous FF

  19. Synchronous Set/Reset Flip Flops Example: library IEEE; use IEEE.std_logic_1164.all; entity FLIPFLOP is port (D1, D2, reset, clk: in std_logic; Q : out std_logic); end FLIPFLOP; architecture EG of FLIPFLOP is begin process (clk) begin if (clk'event and clk='1') then if reset = '1' then Q <= '0' ; else Q <= D1 xor D2; end if ; end if; end process; end EG; Synchronous reset

  20. Asynchronous Set/Reset Flip Flops • Reset is ON sensitivity list. signal D, Q, clk, reset : bit ; ... process (clk, reset) begin if (reset = ’1’) then Q <= ’0’ ; elsif (clk’event and clk = ’1’) then Q <= D ; end if ; end process ;

  21. Asynchronous Set/Reset Flip Flops And now full Example of asynchronous ff with excitation equation for D: library IEEE; use IEEE.std_logic_1164.all; entity FLIPFLOP is port (D1, D2, reset, clk: in std_logic; Q : out std_logic); end FLIPFLOP; architecture EG of FLIPFLOP is begin process (clk, reset) begin if reset = '1' then Q <= '0' ; elsif (clk'event and clk='1') then Q <= D1 xor D2; end if; end process; end EG;

  22. Clock Enable Flip Flops enable signal D, Q, enable, clk : bit ; ... process (clk) begin if (clk’event and clk=’1’) then if (enable=’1’) then Q <= D ; end if ; end if ; end process ; D Q D clk b4: block (clk’event and clk=’1’) begin Q <= GUARDED D when enable=’1’ else Q ; end block ;

  23. Flip Flops inferred by Wait Until • No sensitivity lists • No asynchronous reset signal D, Q, clk : bit ; ... process begin wait until clk’event and clk=’1’ ; Q <= D ; end process ; D D Q clk

  24. Avoid undesired memory elements • Assign values to variables before using them: a := b and c; d := a or b; -- combinational network • Assign value in each branch to signals • Assign value to signals at the beginning of the process

  25. Flip Flops inferred by Variables • We obtain a 3 bits shift register • Explain why it is so architecture EG of FLIPFLOP is begin process (clk) variable a,b : std_logic; begin if (clk'event and clk='1') then Q <= b; b := a; a := D; end if; end process; end EG; This assignment of signal needs to have a FF with output a Here variable b has no value, it is created only after a has value and a only after D has value This is strange For every variable we have a ff.

  26. Flip Flops inferred by Variables • Variable assignment order – FF created when assigned before use. architecture EG of FLIPFLOP is begin process (clk) variable a,b : std_logic; begin if (clk'event and clk='1') then a := D; b := a; Q <= b; end if; end process; end EG; The only difference here is order of assignments in process, here we have variable assignments first. Remember that variables are assigned immediately

  27. Edge Synchronization using function RISING_EDGE Synchronized D Flip-Flop Edge Detection: Clock in sensitivity list...If CLK’EVENT and CLK=‘1’ then ... Process with no sensitivity list:...wait until CLK’EVENT and CLK = ‘1’ • In simulation: ‘X’ -> ‘1’ ??? FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS BEGIN RETURN (s'EVENT AND (To_X01(s) = '1') AND (To_X01(s'LAST_VALUE)='0')); END; Here we declare function rising_edge

  28. Flip-flop with synchronous reset entity dFF is port(Reset: in Bit; D : in Bit; Clk : in Bit; Q : out Bit); end dFF; architecture dFF_a of dFF is begin dFF_Lbl: process(Clk) begin if Clk'event and Clk='1' then if Reset = '1' then Q <= '0'; else Q <= D; end if; end if; end process dFF_Lbl; end dFF_a; Earlier we showed another way of using synchronous reset

  29. Asynchronous set and reset entity dFF is port(Reset: in Bit; D : in Bit; Clk : in Bit; Q : out Bit); end dFF; architecture dFF_a of dFF is begin dFF_Lbl: process(Clk, Reset) begin if Reset = '1' then Q <= '0'; elsif Clk'event and Clk='1' then Q <= D; end if; end process dFF_Lbl; end dFF_a;

  30. Why so many FF syntax? • Highlight the importance of writing good HDL code • Coding style affects synthesized structure directly • Internal working of synthesizers

  31. Descriptions of Tristate Buffers • 3 output states: 0, 1, Z (high impedance) entity tristate is port ( D, en: in std_logic ; Q : out std_logic); end tristate ; architecture EG of tristate is begin Q <= D when en = ’1’ else ’Z’ ; end EG ; p1 : process (en, D) begin if (en=’1’) then Q <= D ; else Q <= ’Z’ ; end if ; end process ; Observe that because I used symbol Z the system inferred tri-state circuit by itslef

  32. Description of wired circuit using Tristate Buffers • Simultaneous assignment to 1 signal • Does not verify exclusivity We do not specify if this is wired OR or wired AND or what library IEEE; use IEEE.std_logic_1164.all; entity tristate is port ( D1, D2 , en1, en2 : in std_logic ; Q : out std_logic); end tristate ; architecture EG of tristate is begin Q <= D1 when en1 = '1' else 'Z' ; Q <= D2 when en2 = '1' else 'Z' ; end EG ;

  33. Flip-flops with Tristate Buffers • If output of FF or latch is tristated, enable line is also tristated. entity tristate is port ( D, en, clk: in std_logic ; Q : out std_logic); end tristate ; architecture EG of tristate is begin process (en, clk) begin if (en = '0') then Q <= 'Z'; elsif (clk'event and clk = '1') then Q <= D; end if; end process; end EG ; This is one more argument for using standard logic STD_LOGIC

  34. Tri-State Buffer at the FF’s output Avoid FF in the path to control the buffer architecture DTri_enff of DTri is begin DTri_Lbl: process(Clk) begin if Clk'event and Clk = '1' then if TriEnb = ‘0' then Dout <= 'Z'; else Dout <= Din; end if; end if; end process DTri_Lbl; end DTri_enff;

  35. Tri-State Buffer at the FF’s output library IEEE; use IEEE.Std_Logic_1164.all; entity DTri is port(TriEnb : in Std_Logic; Din : in Std_Logic; Clk : in Std_Logic; Dout : out Std_Logic); end DTri; architecture DTri_encom of DTri is begin DTri_Lbl: process(Clk, TriEnb) begin if TriEnb = ‘0' then Dout <= 'Z'; elsif Clk'event and Clk = '1' then Dout <= Din; end if; end process DTri_Lbl; end DTri_encom;

  36. Busses with tri-state buffers • Use arrays in the declarations entity tristate is port ( D1, D2: in std_logic_vector (7 downto 0); en1, en2 : in std_logic; Q : out std_logic_vector (7 downto 0) ); end tristate ; architecture EG of tristate is begin Q <= D1 when en1 = '1' else "ZZZZZZZZ" ; Q <= D2 when en2 = '1' else "ZZZZZZZZ" ; end EG ; This description and circuit describes selector circuit realized with tri-state buffers on a bus – this is an important circuit