1 / 42

Sequential Circuit Synthesis

Sequential Circuit Synthesis. Virendra Singh Indian Institute of Science Bangalore. IEP on Digital System Synthesis IIT Kanpur. Computer Hardware = Datapath + Control. Concept of the State Machine. Qualifiers. Registers Combinational Functional Units (e.g., ALU) Buses.

garrison-baxter
Télécharger la présentation

Sequential Circuit Synthesis

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Sequential Circuit Synthesis Virendra Singh Indian Institute of Science Bangalore IEP on Digital System Synthesis IIT Kanpur

  2. Computer Hardware = Datapath + Control Concept of the State Machine Qualifiers Registers Combinational Functional Units (e.g., ALU) Buses FSM generating sequences of control signals Instructs datapath what to do next Control "Puppeteer who pulls the strings" Control State Control Signal Outputs Qualifiers and Inputs Datapath "Puppet" Sequential@iitk

  3. Serial Adder Adder X1 Z X2 X1 0 1 1 0 0 X2 0 1 1 1 0 -------------------------- Z 1 1 0 1 0 Sequential@iitk

  4. 11/0 01/1 00/0 10/1 A B Serial Adder 01/0 10/0 11/1 00/1 Sequential@iitk

  5. Serial Adder Sequential@iitk

  6. R Q Q’ S Memory Elements Sequential@iitk

  7. SR FF RS = 0 Q(t+1) = R’Q(t) + S Sequential@iitk

  8. SR FF Excitation Table Sequential@iitk

  9. JK FF Excitation Table Sequential@iitk

  10. T FF Excitation Table Sequential@iitk

  11. D FF Excitation Table Sequential@iitk

  12. Serial Adder Sequential@iitk

  13. Serial Adder Y = x1x2 + x1y + x2y Z = x1’x2’y + x1’x2y’ + x1x2’y’ +x1x2y Sequential@iitk

  14. Basic Design Approach Six Step Process 1. Understand the statement of the Specification 2. Obtain an abstract specification of the FSM 3. Perform a state minimization 4. Perform state assignment 5. Choose FF types to implement FSM state register 6. Implement the FSM Sequential@iitk

  15. Basic Design Approach Example:Vending Machine FSM General Machine Concept: • deliver package of gum after 15 cents deposited • single coin slot for dimes, nickels • no change Step 1. Understand the problem Draw a picture! Block Diagram Sequential@iitk

  16. Vending Machine Example Step 2. Map into more suitable abstract representation Tabulate typical input sequences: three nickels nickel, dime dime, nickel two dimes two nickels, dime Draw state diagram: Inputs: N, D, reset Output: open Sequential@iitk

  17. Vending Machine Example Step 3: State Minimization reuse states whenever possible Symbolic State Table Sequential@iitk

  18. Vending Machine Example Step 4: State Encoding Sequential@iitk

  19. Vending Machine Example Step 5. Choose FFs for implementation D FF - easiest to use D1 = Q1 + D + Q0 N D0 = N Q0 + Q0 N + Q1 N + Q1 D OPEN = Q1 Q0 8 Gates Sequential@iitk

  20. Vending Machine Example Step 5. Choosing FF for Implementation J-K FF Remapped encoded state transition table Sequential@iitk

  21. Vending Machine Example Implementation: J1 = D + Q0 N K1 = 0 J0 = Q0 N + Q1 D K0 = Q1 N 7 Gates Sequential@iitk

  22. Modulo 6 Counter - Specification • A module 6 counter is a 3-bit counter that counts through the following sequence: • 000->001->010->011->100->101->000->… • 0 -> 1 -> 2 -> 3 -> 4 -> 5 -> 0 … • It doesn’t use value 6 (110) nor 7 (111) • It has an input U that controls the counter: • When U=1 the counter increments its value on the rising edge of the clock • When U=0 the counter retains its value on the rising edge of the clock • The value of the count is represented as three bit value (V2V1V0) • There is an additional output C (Carry) that is 1 when going from 5 to 0 and 0 otherwise (the C output remains 1 until the counter goes from 0 to 1) Sequential@iitk

  23. Modulo 6 Counter – State table • For each state examine what happens for all possible values of the inputs • In state S0 input U can be either 0 or 1 • If U=0 the state machine remains in state S0 and outputs C=1 and V2V1V0=000 • If U=1 the state machine goes in state S1, outputs C=1 and V2V1V0=001 • In the same manner, each state goes to the next state if U=1 and remains in the same state if U=0 Sequential@iitk

  24. Modulo 6 Counter - Mealy state diagram • The outputs are represented on the arcs as CV2V1V0 Sequential@iitk

  25. Modulo 6 Counter – Moore state diagram • The outputs are represented adjacent to the state • The inputs are represented on the arcs Sequential@iitk

  26. Assigning State Values • Each state must be assigned to a unique binary value; for a machine with n states we have [log2n] bits; • For the modulo 6 counter example, we have six states. We will assign state value 000 to S0, 001 to S1, and so on, up to 101 to S5. Sequential@iitk

  27. Assigning State Values • Any values can be assigned to the states, some values can be better than others (in terms of minimizing the logic to create the output and the next state values) • This is actually an iterative process: first the designer creates a preliminary design to generate the outputs and the next states, then modifies the state values and repeats the process. There is a rule of thumb, that simplifies the process: whenever possible, the state should be assigned the same with the output values associated with that state. In this case, same logic can be used to generate the next state and the output Sequential@iitk

  28. Mealy and Moore Machine Implementations • The current state value is stored into the register • The state value together with the machine inputs, are input to a logic block (CLC) that generates the next state value and machine outputs • The next state is loaded into the register on the rising edge of the clock signal Sequential@iitk

  29. Mod 6 Counter – Mealy Implementation • The logic block (CLC) is specific to every system and may consist of combinatorial logic gates, multiplexers, lookup ROMs and other logic components • The logic block can’t include any sequential components, since it must generate its value in one clock cycle • The logic block contains two parts: • One that generates the outputs (f function, CLC1) • One that generates the next state (g function, CLC2) Sequential@iitk

  30. Mod 6 Counter – Moore Implementation • The outputs depend only on the present state and not on its inputs • Its configuration is different than the Mealy machine • The system output depends only on the present state, so the implementation of the output logic is done separately • The next state is obtained from the input and the present state (same as for the Mealy machine) Sequential@iitk

  31. Generating the Next State • Since the Mealy and Moore machines must traverse the same states under the same conditions, their next state logic is identical • We will present three methods to generate the next state logic: • (i) Combinatorial logic gates • (ii) Using multiplexers • (iii) Using lookup ROM • To begin with, we need to setup the truth table for the next state logic Sequential@iitk

  32. Modulo 6 Counter - Next State Logic • The system inputs and the present states are the inputs of the truth table • Next state bits are the outputs • We have to construct a Karnaugh map for each output bit and obtain its equation • After that we design the logic to match the equations Sequential@iitk

  33. Modulo 6 Counter – Next State Logic • N2 = P2P0’ + P2U’ +P1P0U • N1 = P1P0’ + P1U’ + P2’P1’P0U • N0 = P0’U + P0U’ Sequential@iitk

  34. Modulo 6 Counter – Next State implementation using logic gates (i) Sequential@iitk

  35. State Minimization X-Successor – If an input sequence X takes a machine from state Si to state Sj, then Sj is said to be the X-successor of Sj Strongly connected:- If for every pair of states Si, Sj of a machine M there exists an input sequence which takes M from state Si to Sj, then M is said to be strongly connected Sequential@iitk

  36. State Equivalence • Two states Si and Sj of machine M are distinguishable if and only if there exists at least one finite input sequence which, when applied to M, causes different output sequences, depending on whether Si or Sj is the initial state • The sequence which distinguishes these states is called a distinguishing sequence of the pair (Si, Sj) • If there exists for pair (Si, Sj ) a distinguishing sequence of length k, the states in (Si, Sj ) are said to be k-distinguishable Sequential@iitk

  37. State Equivalence (A, B) – 1 Distinguishable (A, E) – 3 Distinguishable Seq - 111 Machine M1 k-equivalent – The states that are not k-distinguishable are said to be k-equivalent Also r-equivalent r<k Sequential@iitk

  38. State Equivalence • States Si and Sj of machine M are said to be equivalent if and only if, for every possible input sequence, the same output sequence will be produced regardless of whether Si or Sj is the initial state • States that are k-equivalent for all k < n-1, are equivalent • Si = Sj, and Sj=Sk, then Si=Sk Sequential@iitk

  39. State Equivalence • The set of states of a machine M can be partitioned into disjoint subsets, known as equivalence classes • Two states are in the same equivalence class if and only if they are euivalent, and are in different classes if and only if they are distinguishable Property: If Si and Sj are equivalent states, their corresponding X-successors, for all X, are also equivalent Sequential@iitk

  40. State Minimization Procedure • Partion the states of M into subsets s.t. all states in same subset are 1-equivalent • Two states are 2-equivalent iff they are 1-equivalent and their Ii successors, for all possible Ii, are also 1-equivalent P0 = (ABCDEF) P1 = (ACE), (BDF) P2 = (ACE), (BD), (F) P3 = (AC), (E), (BD), (F) P4 = (AC), (E), (BD), (F) Sequential@iitk

  41. Machine Equivalence • Two machines M1, M2 are said to be equivalent if and only if, for every state in M1, there is corresponding equivalent state in M2 • If one machine can be obtained from the other by relabeling its states they are said to be isomorphic to each other δ Sequential@iitk

  42. Example P0 = (ABCDEFG) P1 = (ABCDFG) (E) P2 = (AF) (BCDG) (E) P3 = (AF) (BD) (CG) (E) P4 = (A) (F) (BD) (CG) (E) P5 = (A) (F) (BD) (CG) (E) Machine M2 Sequential@iitk

More Related