Lecture 12 PicoBlaze Overview

1. Lecture 12PicoBlaze Overview ECE 448 – FPGA and ASIC Design with VHDL

2. Required reading • P. Chu, FPGA Prototyping by VHDL Examples • Chapter 14, PicoBlaze Overview • Chapter 15, PicoBlaze Assembly Code Development Recommended reading PicoBlaze 8-bit Embedded Microcontroller User Guide for Spartan-3, Virtex-II, and Virtex-II Pro FPGAs (search for it using Google or Xilinx website documentation search) ECE 448 – FPGA and ASIC Design with VHDL

3. Block diagram of a Single-Purpose Processor (FSMD – Finite State Machine with Datapath) ctrl ECE 448 – FPGA and ASIC Design with VHDL

4. Block diagram of a General-Purpose Processor (Microcontroller) ECE 448 – FPGA and ASIC Design with VHDL

5. PicoBlaze ECE 448 – FPGA and ASIC Design with VHDL

6. PicoBlaze Overview

7. Register File of PicoBlaze 8-bit Address s0 s1 s2 s3 s4 s5 s6 s7 0 7 0 1 0 7 2 7 0 3 7 0 4 7 0 5 7 0 16 Registers 7 0 6 7 0 7 sf F 7 0

8. Definition of Flags Flags are set or reset after ALU operations Zero flag - Z zero condition Z = 1 if result = 0 0 otherwise overflow, underflow, or various conditions Carry flag - C Example* C = 1 if result > 28-1 or result < 0 0 otherwise *Applies only to addition or subtraction related instructions, refer to following slides otherwise

9. Interface of PicoBlaze KCPSM = constant (K) coded programmable state machine ECE 448 – FPGA and ASIC Design with VHDL

10. Interface of PicoBlaze ECE 448 – FPGA and ASIC Design with VHDL

11. Development Flow of a System with PicoBlaze ECE 448 – FPGA and ASIC Design with VHDL

12. PicoBlaze Programming Model ECE 448 – FPGA and ASIC Design with VHDL

13. Syntax and Terminology Syntax Example Definition sX KK PORT(KK) PORT((sX)) RAM(KK) Value at register 7 Value ab (in hex) Input value from port 2 Input value from port specified by register a Value from RAM location 4 s7 ab PORT(2) PORT((sa)) RAM(4)

14. Addressing modes Immediate mode ADDCY s2, 08 SUB s7, 7 s2 + 08 + C  s2 s7 – 7  s7 Direct mode PORT(2a)  s5 sa + sf  sa INPUT s5, 2a ADD sa, sf Indirect mode PORT((s2))  s9 s3 RAM((sa)) INPUT s9, (s2) STORE s3, (sa)

15. PicoBlaze ALU Instruction Set Summary (1)

16. PicoBlaze ALU Instruction Set Summary (2)

17. PicoBlaze ALU Instruction Set Summary (3)

18. Logic instructions C Z • AND • AND sX, sY • sX and sY => sX • AND sX, KK • sX and KK => sX • 2. OR • OR sX, sY • sX or sY => sX • OR sX, KK • sX or KK => sX • 3. XOR • XOR sX, sY • sX xor sY => sX • XOR sX, KK • sX xor KK => sX 0 IMM, DIR 0 IMM, DIR IMM, DIR 0

19. Arithmetic Instructions (1) C Z IMM, DIR Addition ADD sX, sY sX + sY => sX ADD sX, KK sX + KK => sX ADDCY sX, sY sX + sY + CARRY => sX ADDCY sX, KK sX + KK + CARRY => sX

20. Arithmetic Instructions (2) C Z IMM, DIR Subtraction SUB sX, sY sX – sY => sX SUB sX, KK sX – KK => sX SUBCY sX, sY sX – sY – CARRY => sX SUBCY sX, KK sX – KK – CARRY => sX

21. Test and Compare Instructions C Z TEST TEST sX, sY sX and sY => none TEST sX, KK sX and KK => none COMPARE COMPARE sX, sY sX – sY => none COMPARE sX, KK sX – KK => none IMM, DIR C = odd parity of the result IMM, DIR

22. Data Movement Instructions (1) C Z - - LOAD LOAD sX, sY sY => sX LOAD sX, KK KK => sX IMM, DIR

23. Data Movement Instructions (2) C Z - - DIR, IND STORE STORE sX, KK sX => RAM(KK) STORE sX, (sY) sX => RAM((sY)) - - DIR, IND FETCH FETCH sX, KK RAM(KK) => sX FETCH sX, (sY) RAM((sY)) => sX

24. Data Movement Instructions (3) C Z - - DIR, IND INPUT INPUT sX, KK sX <= PORT(KK) INPUT sX, (sY) sX <= PORT((sY)) OUTPUT OUTPUT sX, KK PORT(KK) <= sX OUTPUT sX, (sY) PORT((sY)) <= sX - - DIR, IND

25. Edit instructions - Shifts *All shift instructions affect Zero and Carry flags

26. Edit instructions - Rotations *All rotate instructions affect Zero and Carry flags

27. Program Flow Control Instructions (1) JUMP AAA PC <= AAA JUMP C, AAA if C=1 then PC <= AAA else PC <= PC + 1 JUMP NC, AAA if C=0 then PC <= AAA else PC <= PC + 1 JUMP Z, AAA if Z=1 then PC <= AAA else PC <= PC + 1 JUMP NZ, AAA if Z=0 then PC <= AAA else PC <= PC + 1

28. Program Flow Control Instructions (2) CALL AAA TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA CALL C | Z , AAA if C | Z =1 then TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA else PC <= PC + 1 CALL NC | NZ , AAA if C | Z =0 then TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA else PC <= PC + 1

29. Program Flow Control Instructions (3) RETURN PC <= STACK[TOS] + 1; TOS <= TOS - 1 RETURN C | Z if C | Z =1 then PC <= STACK[TOS] + 1; TOS <= TOS - 1 else PC <= PC + 1 RETURN NC | NZ if C | Z =0 then PC <= STACK[TOS] + 1; TOS <= TOS - 1 else PC <= PC + 1

30. Subroutine Call Flow

31. Interrupt Related Instructions RETURNI ENABLE PC <= STACK[TOS] ; TOS <= TOS – 1; I <= 1; C<= PRESERVED C; Z<= PRESERVED Z RETURNI DISABLE PC <= STACK[TOS] ; TOS <= TOS – 1; I <= 0; C<= PRESERVED C; Z<= PRESERVED Z ENABLE INTERRUPT I <=1; DISABLE INTERRUPT I <=0;

32. Interrupt Flow ECE 448 – FPGA and ASIC Design with VHDL

33. PicoBlaze Development Environments ECE 448 – FPGA and ASIC Design with VHDL

34. KCPSM3 Assembler Files ECE 448 – FPGA and ASIC Design with VHDL

35. Directives of Assembly Language Equating symbolic name for an I/O port ID. keyboard DSIN $0E switch DSIN $0F LED DSOUT $15 N/A ECE 448 – FPGA and ASIC Design with VHDL

36. Differences between Mnemonics of Instructions ECE 448 – FPGA and ASIC Design with VHDL

37. Differences between Mnemonics of Instructions ECE 448 – FPGA and ASIC Design with VHDL

38. Differences between Programs ECE 448 – FPGA and ASIC Design with VHDL