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Processor Power Management Overview

Processor Power Management Overview . Agenda. Introduction Overview of all power states Global States Device States CPU States PCIe Link PM States Sleep States AMT States. Agenda. Introduction Overview of all power states Global States

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Processor Power Management Overview

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  1. Processor Power Management Overview

  2. Agenda • Introduction • Overview of all power states • Global States • Device States • CPU States • PCIe Link PM States • Sleep States • AMT States

  3. Agenda • Introduction • Overview of all power states • Global States • Device States • CPU States • PCIe Link PM State • Sleep States • Reset • Backup

  4. Power Management under ACPI • Advanced Configuration and Power Management Interface • New concepts beyond APM • Fine granularity on CPU clock control • Multiple system sleeping states • Individual device management without H/W traps and timers • Thermal Management • Primary methodology for current power management. • Define Power States within the platform. • Lx States : Link States (for DMI and PEG) • Dx States : Device States • Cx States : CPU States. • Sx States : Sleep (System) States. • Mx States : ME (AMT)States. • Gx States : Global States.

  5. Agenda • Introduction • Overview of all power states • Global States • Device States • CPU States • PCIe Link PM States • Sleep States • Reset • Backup

  6. Individual devices can be in Dx and processor can be in Cx • G0/S0/C0: Full On • G0/S0/C1: Auto Halt • G0/S0/C2: Stop Grant • G0/S0/C3: Stop Clock • G0/S0/C4: Stop Clock with lower CPU voltage • G0/S0/C5 : Stop Clock with partial power off G1/S1: Stop Grant G1/S3: Suspend to ram (STR) G1/S4: Suspend to Disk (STD) G2/S5: Soft Off G3 : no power at all ( no battery or the system is insufficient supply level to wake) • G0(Working State) • - System is running • - Power is on Sleep / Hibernate Wake event • G1(Sleeping State) • No System Traffic • MCH, ICH and CPU off OS initiate Power off PWR plug in & AFTERG3_EN=0 • G2(Soft Off) • - No System Traffic • - System is off • - Small part of ICH remains on to accept • wake up event. • G3(Mech. Off) • System is unplugged • RTC battery continues • to supply power to RTC PWR plug in & AFTERG3_EN=1 Global system state

  7. Agenda • Introduction • Overview of all power states • Global States • Device States • CPU States • PCIe Link PM States • Sleep States • Reset • Backup

  8. Device States : General D0 Fully-On • This state is assumed to be the highest level of power consumption. The device is completely active. D1 - D2 Optional. Expected to save more power and preserve less device context than D0. D2 save more power than D1 but the latency is high. D3 Off - Power has been fully removed from the device. The device context is lost when this state is entered, so the OS software will reinitialize.

  9. Agenda • Introduction • Overview of all power states • Global States • Device States • CPU States • PCIe Link PM States • Sleep States • Reset • Backup

  10. CPU States : General C0 Processor Power State • Normal state. While the processor is in this state, it executes instructions. C1-C5 Processor Power State • Non executing power state. • The deeper the C state, the lower the power consumed by the processor in that state. • Processor power in C1 is higher than the processor power in C4. • The deeper the C state, the higher the entry and exit latency of that state • Entry/exit latency of C4 is higher than that of C1

  11. Intel CPU States

  12. Intel CPU States

  13. Intel® Deep Power Down Technology (C6) Flexible C-States to Select Idle Power Level vs. Responsiveness

  14. C2 Entry/Exit Sequences Note: “M-I link” is DMI. “SG” message on “M-I link” should be “Req-C2”

  15. C3 Entry Sequences

  16. C3 Exit Sequences

  17. C4 Entry Sequences

  18. C4 Exit Sequences

  19. C5/C6 Entry Sequences

  20. C5/C6 Exit Sequences

  21. NHM CPU States • NHM supports C0, C1, C1E, C3, C6 and C7. • C7 is identical to C6 at core level but different Uncore power optimization. • C7 is an overall package state where all cores have lost their registers, last level cache is at its minimum voltage but uncore is still in retention voltage • On NHM, STPCLK#, SLP# and DPSLP# signals are removed due to platform change and CSI bus interface. • Not all package C-state will be supported on all versions of NHM like Uncore power reduction features on C3 and lower power states maybe fused off in desktop or server parts.

  22. Agenda • Introduction • Overview of all power states • Global States • Device States • CPU States • PCIe Link PM State • Sleep States Reset • Common Questions

  23. Link PM States • L0– Active state • TLP(Transaction Layer Packet)’s and DLLP(Data Link Layer Packet)’s are permitted • L0s– Low resume latency, energy saving “standby” state: • no TLP/DLLP during L0s state • quick entry/exit, exit in the order of 100 ns for Intel chipset • L0s is single-directional. A transmitter can initiate L0s without the other port initiating L0s. • Main power and clocks remain. • Chipset gates some internal logic. • L1– lower power standby state – Higher latency PM state: • Downstream port initiates when the device power state is programmed to non D0 state(D3) • no TLP/DLLP during L1 state. • Main power and clocks remain. • Exit in order of micro seconds.

  24. Link PM States (Contd..) • L2/3 ready – Staging point for L2/L3 – Required for PCIe PM before entering L2 or L3 state, this is not a real link state, it is just a phase requiring protocol handshake before entering L2 or L3. • A device must be in D3state before entering L2/3 ready • System will place link L2/3 ready state before entering S3/S4/S5. • L2– Auxiliary powered Link deep energy state. L2 is optionally supported. • Main power and clks are removed • the device has aux power to perform link reactivation through beacon, WAKE#, PME context and detection logic. • L3– Link off state. Zero power state.

  25. Link PM States (Contd..)Summary of Link PM States:

  26. Link PM States (Contd..)ASPM Control: Allows Hardware controlled PCIe dynamic link power reduction.

  27. Link PM States (Contd..)ASPM Control:

  28. Link PM States (Contd..)Relationship between Link and Device PM State.

  29. System and DMI Link Power States

  30. System and DMI Link Power States

  31. Agenda • Introduction • Overview of all power states • Global States • Device States • CPU States • PCIe Link PM State • Sleep States • Reset • Backup

  32. Sleep States – User Point of View

  33. S0 S0 S1 S1 S3 S3 S4 S4 S5 S5 t53b t53b STPCLK# STPCLK# Go Go - - Ack Ack DMI DMI REQ REQ Go Go - - Ack Ack L2/ L2/ - - C2 C2 C2 C2 - - C2 C2 L3 L3 S3 S3 - - S3 S3 t53c t53c CPUSLP# CPUSLP# SUS_STAT# SUS_STAT# t55 t55 t56 +t58 t56 +t58 PLTRST# PLTRST# t59 t59 SLP_S3# SLP_S3# t60 (for S3 t60 (for S3 - - Cold only) Cold only) PWROK# PWROK# t61 t61 SLP_S4# SLP_S4# t62 t62 SLP_S5# SLP_S5# Sleep State Entry Sequence

  34. Sleep State Exit Sequence

  35. Agenda • Introduction • Overview of all power states • Global States • Device States • CPU States • PCIe Link PM State • Sleep States Reset • AMT Status

  36. ME impact on Sleep States

  37. Thank You

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