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ECE 875: Electronic Devices

This lecture covers the topic of MOSFETs, specifically the channel current IDS in n-channel p-substrate MOSFETs. Examples and theory are discussed, along with the goal of achieving IDS in the charge sheet constant mobility model. The lecture also explores how to achieve higher current and the factors that require fabricating a new device.

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ECE 875: Electronic Devices

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  1. ECE 875:Electronic Devices Prof. Virginia Ayres Electrical & Computer Engineering Michigan State University ayresv@msu.edu

  2. Lecture 33, 02 Apr 14 • Chp 06: MOSFETs • Channel Current IDS (n-channel p-substrate) • Examples • Theory • Goal: IDS in charge sheet constant mobility model, • good for both linear and saturation I-V regimes VM Ayres, ECE875, S14

  3. Lec 32: Answer: Higher current: Goal How to achieve goal VM Ayres, ECE875, S14

  4. You must fabricate a new device if you change: • Gate metallization dimensions: length L or width Z • Oxide (insulator) thickness d or dielectric material eox (ei) • You can keep the same device and change the battery voltages: • The drain to source potential drop VDS = Sze VD • The gate voltage VG (but not the VG = VT value required for full inversion)

  5. Do you have to fabricate a new device? VM Ayres, ECE875, S14 VM Ayres, ECE875, S14

  6. Do you have to fabricate a new device? Answer: YES VM Ayres, ECE875, S14

  7. Channel length L changes, channel width Z stays the same Do you have to fabricate a new device? YES. VM Ayres, ECE875, S14

  8. Channel length L changes, channel width Z stays the same Do you have to fabricate a new device? YES. For gate current IG: VG = IG R“metal” plate Conductance G = 1/Resistance R VM Ayres, ECE875, S14

  9. Channel length L changes, channel width Z stays the same Do you have to fabricate a new device? YES. Reducing the size of the “metal” plate reduces the amount of time on it needed to get a full inversion charge sheet underneath For gate current IG: VG = IG R“metal” plate Conductance G = 1/Resistance R VM Ayres, ECE875, S14

  10. VM Ayres, ECE875, S14

  11. R VM Ayres, ECE875, S14 r h

  12. Let A = Z mn Cox [(VG – VT) VD -1/2 VD2 in ID Take IG1/ID1 and IG2/ID2 to solve for L2 VM Ayres, ECE875, S14

  13. Lecture 33, 02 Apr 14 • Chp 06: MOSFETs • Channel Current IDS (n-channel p-substrate) • Examples • Theory • Goal: IDS in charge sheet constant mobility model, • good for both linear and saturation I-V regimes VM Ayres, ECE875, S14

  14. First check coordinate system: L z Width = Z y: S to D SiO2 x VM Ayres, ECE875, S14

  15. First check coordinate system: L z Width = Z y SiO2 x Chp. 04 Rotated by 90o VM Ayres, ECE875, S14

  16. First check coordinate system:Now rotate forward by 90o: nergy Will plot energy band diagram of the flatband into strong inversion conditions in x-y VM Ayres, ECE875, S14

  17. First check coordinate system: For IDrain to Source for n-channel p-substrate: +y is e- transport direction -y is current IDS transport direction y z x VM Ayres, ECE875, S14

  18. Will plot: The bigger depletion region at the Drain end leads to a physical pinch, which leads to saturation current. IDS free Qn . Qn  Qn(y) VM Ayres, ECE875, S14

  19. Now do 3D version of energy band diagrams at: • Flatband • Strong inversion: VG ON • Strong inversion: VGand VDS ON: IDS now moving VM Ayres, ECE875, S14

  20. Flatband condition: nergy Substrate is p-type right up to gate region VM Ayres, ECE875, S14

  21. Strong inversion: VG ON: nergy Bands are bent in x eventually making channel region EF – Ei n-type. This is uniformly true in y VM Ayres, ECE875, S14

  22. Strong inversion: VGand VDS ON: IDS now moving: Note that VDS = + and ON also puts VDS – VBackOfSubstrate into reverse bias across pn+ junction n-typeness in the channel is bigger at the left than at the right VM Ayres, ECE875, S14

  23. VDS is ON: Getting into saturation regime: nergy Energy picture when VDS is ON: Variations in (EF- Ei) in y VM Ayres, ECE875, S14

  24. VDS is ON: Variations in (EF- Ei) in y n-typeness in the channel is bigger at the left than at the right nergy (y) VM Ayres, ECE875, S14

  25. EC, Ei and EV are carried down since Egap doesn’t change. nergy (y) VM Ayres, ECE875, S14

  26. Use E+: the change DEi = qDyi(y) nergy (y) VM Ayres, ECE875, S14

  27. Find Qn = Qn(y): Charge sheet model Means: when y = L VM Ayres, ECE875, S14

  28. Find Qn = Qn(y): Charge sheet model VM Ayres, ECE875, S14

  29. Therefore: Qn = Qn(y): Charge sheet model VM Ayres, ECE875, S14

  30. Use Qn(y) in:

  31. Additional point: as noted before: Note that VDS = + and ON also puts VDS – VBackOfSubstrate into reverse bias across n+p junction n-typeness in the channel is bigger at the left than at the right Could say: n-typeness in the channel is smaller at the right than at the left VM Ayres, ECE875, S14

  32. Ei and EFn cross: lessening of n-typeness near Drain, then actually p-type, then back to n+ type. nergy (y) VM Ayres, ECE875, S14

  33. Note development of a new depletion region: nergy p-type region exposed to strong E field = depleted of holes (y) VM Ayres, ECE875, S14

  34. Two depletion regions: p-n+ in reverse and the new one: Just p-n+ in reverse depletion region New depletion region and p-n+ in reverse depletion region VM Ayres, ECE875, S14

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