1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות CRC –GENERATOR (Cyclic Redundancy Check) Performed by: Dabran Shalev, Papir Eran Instructor: Orbach Mony Spring 2005

2. Agenda • Goals • Current working system • The new system • CRC Generator and Analyzer • Packet structure • What is CRC? • Schedule

3. Project goals: Developing a 16bit CRC-GENRATOR for the Rocket I/O experiment using to the VirtexII-pro

4. Current System Virtex II-pro BRAM 1 Packet Generation Patterns Traffic Generator Rocket I/O Transceiver PLB BRAM 2 PPC Test Status Storage Traffic Analyzer To PC

5. Virtex II-pro The newsystem BRAM 1 Packet Generation Patterns Traffic Generator CRC Generator Rocket I/O Transceiver PLB BRAM 2 PPC Test Status Storage Traffic Analyzer CRC Analyzer To PC

6. CRC generator • Input : a stream of double word data • Output: the same data + 16 bit CRC

7. CRC Analyzer • Input : a stream of double word data +16 bit CRC • Output: the accepted data and error check

8. Packet structure Current system Header Stamp Stamp Stamp End New system Header Stamp Stamp Stamp CRC End

9. What is CRC? M(x) = Our DATA G(x) = The chosen polynomial n = degree of G(x)

10. Schedule • 4-6 weeks – CRC hardware implementation • 3-5 weeks - integration • 3 weeks – Tests • 4 weeks – documentation

11. THE END