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Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University, Auburn, AL 36849

ELEC 7770 Advanced VLSI Design Spring 2008 A Linear Programming Solution to Clock Constraint Problem. Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html.

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Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University, Auburn, AL 36849

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  1. ELEC 7770Advanced VLSI DesignSpring 2008A Linear Programming Solution to Clock Constraint Problem Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University, Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html ELEC 7770: Advanced VLSI Design (Agrawal)

  2. A General Sequential Circuit Inputs Outputs Combinational Logic Registers Clock ELEC 7770: Advanced VLSI Design (Agrawal)

  3. A Level-Sensitive Latch D QN Q CK Clock period, Tck CK Latch open Latch closed Latch open time ELEC 7770: Advanced VLSI Design (Agrawal)

  4. Alternative Implementation Q D CK J. Segura and C. F. Hawkins, CMOS Electronics, How It Works, How It Fails, Wiley Interscience, 2004, p.137. ELEC 7770: Advanced VLSI Design (Agrawal)

  5. Data Must be Stable Before Latch Closes 0→1→0→0→ 0 1→0→1→0→1→ D = 0 → 1 → 1 1 QN delays 1 Q 0 1 CK = 1 → 1 → 0 0→0→1→0→1→ 1→1→0→0→ Unstable state Clock period, Tck CK Latch open Latch closed time Stable data ELEC 7770: Advanced VLSI Design (Agrawal)

  6. Data and Clock Parameters Clock period, Tck CK Latch open Latch closed time Stable data D time Hold time Setup time Q Stable Q time CK-to-Q delay ELEC 7770: Advanced VLSI Design (Agrawal)

  7. Design With Level-Sensitive Latches PI PI Comb. Logic Comb. Logic Level-sens. Latches Level-sens. Latches PO PO CK ELEC 7770: Advanced VLSI Design (Agrawal)

  8. Edge-Triggered Flip-flop Master latch Slave latch D Q QN CK Hold time Clock period, Tck CK Master open Slave open time Trigger edges Setup time CK-to-Q ELEC 7770: Advanced VLSI Design (Agrawal)

  9. A Dynamic Implementation VDD CK CK D Q CK CK GND J. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and Simulation, Thomsom, 2006, p. 229. ELEC 7770: Advanced VLSI Design (Agrawal)

  10. A Static Implementation VDD Q CK CK D CK CK GND J. P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and Simulation, Thomsom, 2006, p. 230. ELEC 7770: Advanced VLSI Design (Agrawal)

  11. Design With Edge-Triggered Flip-Flops Inputs Outputs Combinational Logic Flip-flops Clock ELEC 7770: Advanced VLSI Design (Agrawal)

  12. Setup Time Constraint Skew si Skew sj Combinational path delay Arrive no later than this FF i FF j δ(i,j) ≤ d(i,j) ≤ Δ(i,j) Note: All times for a FF should be adjusted by its clock skew. Travel time Tsi Thi Tsj time Tqi Tck Clock edge Constraint: si + Tqi + Δ(i,j) ≤ sj + Tck – Tsj i.e., Δ(i,j) ≤ Tck – Tsj – Tqi + sj – si This is known as long path constraint – prevents zero clocking ELEC 7770: Advanced VLSI Design (Agrawal)

  13. Hold Time Constraint Combinational path delay Skew si Skew sj FF i FF j δ(i,j) ≤ d(i,j) ≤ Δ(i,j) Note: All times for a FF should be adjusted by its clock skew. Thj Tsi Thi Tsj time Tqi Tck Clock edge Constraint: si + Tqi + δ(i,j) ≥ sj + Thj i.e., δ(i,j) ≥ Thj – Tqi + sj – si This is known as short path constraint – avoids double clocking ELEC 7770: Advanced VLSI Design (Agrawal)

  14. Solving Hold Time Problem (1) PO (FFj) PI (FFi) PO PI PO (FFi) PI (FFj) Fanout node Internal edges (fixed delays) External edges (variable delays) ELEC 7770: Advanced VLSI Design (Agrawal)

  15. Solving Hold Time Problem (2) • Variables: • Earliest arrival time at node i = ai • Longest arrival time at node i = Ai • Buffer delay on external edge (i,j) = wij • Constants: • At PI i: Ai = Λi and ai = λi, user specified. • At PI (FF) i: Ai = ai = Tqi ELEC 7770: Advanced VLSI Design (Agrawal)

  16. Solving Hold Time Problem (3) • Constraints: • At PO i: Ai ≤ Ri and ai ≥ ri, user defined. • At PO (FF) i: • ai ≥ Thi, short path constraint. • Ai ≤ Tck – Tsi, long path constraint. • Optimization function (a linear approximation to minimum number of delay buffers): minimize ∑ wij all external edges (i,j) ELEC 7770: Advanced VLSI Design (Agrawal)

  17. Linear Programming Solution (1) minimize ∑ wij all external edges (i,j) Subject to: Aj ≥ Ai + wij for all i ε Fanin(j) aj ≤ ai + wij for all i ε Fanin(j) Ai ≤ Ri for all i ε PO ai ≥ ri for all i ε PO Ai ≤ Tck – Tsi for all i ε PO(FF i) ai ≥ Thi for all i ε PO(FF i) Ai = Λi for all i ε PI ai = λi for all i ε PI Ai = Tqi for all i ε PI(FF i) ai = Tqi for all i ε PI(FF i) ELEC 7770: Advanced VLSI Design (Agrawal)

  18. Linear Programming Solution (2) • Solution inserts smallest delays in interconnects to satisfy short path constraints. • Maintains the specified clock period and satisfies setup time constraints. Reference: N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999. ELEC 7770: Advanced VLSI Design (Agrawal)

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