Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

1. ELEC 5270-001/6270-001(Fall 2006)Low-Power Design of Electronic CircuitsPower Analysis: Logic Level Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC 5270-001/6270-001 Lecture 9

2. Power Analysis • Motivation: • Specification • Optimization • Reliability • Applications • Design analysis and optimization • Physical design • Packaging • Test ELEC 5270-001/6270-001 Lecture 9

3. Abstraction, Complexity, Accuracy ELEC 5270-001/6270-001 Lecture 9

4. Spice • Circuit/device level analysis • Circuit modeled as network of transistors, capacitors, resistors and voltage/current sources. • Node current equations using Kirchhoff’s current law. • Average and instantaneous power computed from supply voltage and device current. • Analysis is accurate but expensive • Used to characterize parts of a larger circuit. • Original references: • L. W. Nagel and D. O. Pederson, “SPICE – Simulation Program With Integrated Circuit Emphasis,” Memo ERL-M382, EECS Dept., University of California, Berkeley, Apr. 1973. • L. W. Nagel, SPICE 2, A Computer program to Simulate Semiconductor Circuits, PhD Dissertation, University of California, Berkeley, May 1975. ELEC 5270-001/6270-001 Lecture 9

5. Ca Logic Model of MOS Circuit VDD pMOS FETs a Da c Dc a b Db c Cc b Daand Dbare interconnect or propagation delays Dcis inertial delay of gate Cb nMOS FETs Cd Ca , Cb , Cc and Cd are node capacitances ELEC 5270-001/6270-001 Lecture 9

6. Spice Characterization of a 2-Input NAND Gate ELEC 5270-001/6270-001 Lecture 9

7. Spice Characterization (Cont.) ELEC 5270-001/6270-001 Lecture 9

8. Switch-Level Partitioning • Circuit partitioned into channel-connected components for Spice characterization. • Reference: R. E. Bryant, “A Switch-Level Model and Simulator for MOS Digital Systems,” IEEE Trans. Computers, vol. C-33, no. 2, pp. 160-177, Feb. 1984. G2 Internal switching nodes not seen by logic simulator G3 G1 ELEC 5270-001/6270-001 Lecture 9

9. Delay and Discrete-Event Simulation(NAND gate) Transient region a Inputs b c (CMOS) c (zero delay) c (unit delay) Logic simulation X rise=5, fall=5 c (multiple delay) Unknown (X) c (minmax delay) min =2, max =5 5 Time units 0 ELEC 5270-001/6270-001 Lecture 9

10. Event-Driven Simulation(Example) Activity list d, e f, g g Scheduled events c = 0 d = 1, e = 0 g = 0 f = 1 g = 1 a =1 e =1 t = 0 1 2 3 4 5 6 7 8 2 c =1→0 g =1 2 2 d = 0 Time stack 4 f =0 b =1 g 8 4 0 Time, t ELEC 5270-001/6270-001 Lecture 9

11. Time Wheel (Circular Stack) max Current time pointer t=0 Event link-list 1 2 3 4 5 6 7 ELEC 5270-001/6270-001 Lecture 9

12. Gate-Level Power Analysis • Pre-simulation analysis: • Partition circuit into channel connected gate components. • Determine node capacitances from layout analysis (accurate) or from wire-load model* (approximate). • Determine dynamic and static power from Spice for each gate. • Determine gate delays using Spice or Elmore delay analysis. * Wire-load model estimates of a net by its pin-count. See Yeap, p. 39. ELEC 5270-001/6270-001 Lecture 9

13. Elmore Delay Model 2 • W. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19, no.1, pp. 55-63, Jan. 1948. R2 C2 1 R1 s 4 R4 C4 C1 R3 3 R5 Shared resistance: R45 = R1 + R3 R15 = R1 R34 = R1 + R3 C3 5 C5 ELEC 5270-001/6270-001 Lecture 9

14. Elmore Delay Formula N Delay at node k = 0.69 ΣCj × Rjk j=1 where N = number of capacitive nodes in the network Example: Delay at node 5 = 0.69[R1 C1 + R1 C2 + (R1+R3)C3 + (R1+R3)C4 (R1+R3+R5)C5] ELEC 5270-001/6270-001 Lecture 9

15. Gate-Level Power Analysis (Cont.) • Run discrete-event (event-driven) logic simulation with a set of input vectors. • Monitor the toggle count of each net and obtain capacitive power dissipation: Pcap=ΣCk V 2f all nodes k • Where: • Ckis the total node capacitance being switched, as determined by the simulator. • V is the supply voltage. • f is the clock frequency, i.e., the number of vectors applied per unit ELEC 5270-001/6270-001 Lecture 9

16. Gate-Level Power Analysis (Cont.) • Monitor dynamic energy events at the input of each gate and obtain internal switching power dissipation: Pint = ΣΣ E(g,e) f(g,e) gates g events e • Where • E(g,e) = energy of event e of gate g pre-computed from Spice. • F(g,e) = occurrence frequency of the event e at gate g observed by logic simulation. ELEC 5270-001/6270-001 Lecture 9

17. Gate-Level Power Analysis (Cont.) • Monitor the static power dissipation state of each gate and obtain the static power dissipation: Pstat = ΣΣP(g,s) T(g,s)/ T gates g states s • Where • P(g,s) = static power dissipation of gate g for state s, obtained from Spice. • T(g,s) = duration of state s at gate g, obtained from logic simulation. • T = vector period. ELEC 5270-001/6270-001 Lecture 9

18. Gate-Level Power Analysis (Cont.) • Sum up all three components of power: P = Pcap + Pint + Pstat • References: • A. Deng, “Power Analysis for CMOS/BiCMOS Circuits,” Proc. International Workshop Low Power Design, 1994. • J. Benkoski, A. C. Deng, C. X. Huang, S. Napper and J. Tuan, “Simulation Algorithms, Power Estimation and Diagnostics in PowerMill,” Proc. PATMOS, 1995. • C. X. Huang, B. Zhang, A. C. Deng and B. Swirski, “The Design and Implementation of PowerMill,” Proc. International Symp. Low Power Design, 1995, pp. 105-109. ELEC 5270-001/6270-001 Lecture 9