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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

ELEC 5970-003/6970-003 (Fall 2004) Advanced Topics in Electrical Engineering Designing VLSI for Low-Power and Self-Test Power Consumption in a CMOS Circuit. Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

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  1. ELEC 5970-003/6970-003 (Fall 2004)Advanced Topics in Electrical EngineeringDesigning VLSI for Low-Power and Self-TestPower Consumption in a CMOS Circuit Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC 5970-003/6970-003

  2. Motivation • Low power applications • Remote systems (e.g., satellite) • Portable systems (e.g., mobile phone) • Methods of low power design • Reduced supply voltage • Adiabatic switching • Clock suppression • Logic design for reduced activity • Reduce Hazards (40% in arithmetic logic) • Software techniques • Reference: Chandrakasan and Brodersen ELEC 5970-003/6970-003

  3. Low-Power Design • Design practices that reduce power consumption at least by one order of magnitude; in practice 50% reduction is often acceptable. • General topics • High-level and software techniques • Gate and circuit-level methods • Power estimation techniques • Test power ELEC 5970-003/6970-003

  4. 10000 1000 Rocket Sun’s Surface Nozzle 100 Nuclear Power Density (W/cm2) Reactor 8086 10 4004 P6 Hot Plate 8008 Pentium® 8085 386 286 486 8080 1 1970 1980 1990 2000 2010 Year VLSI Chip Power Density Source: Intel ELEC 5970-003/6970-003

  5. Specific Topics on Low-Power • Power dissipation in CMOS circuits • Low-power CMOS technologies • Dynamic reduction techniques • Leakage power • Power estimation ELEC 5970-003/6970-003

  6. Components of Power • Dynamic • Signal transitions • Logic activity • Glitches • Short-circuit • Static • Leakage ELEC 5970-003/6970-003

  7. VDD Ground Power of a Transition isc Power = CLVDD2/2 + Psc R Vo Vi CL R ELEC 5970-003/6970-003

  8. Short Circuit Current, isc(t) VDD VDD - VTp Vi(t) Volt Vo(t) VTn 0 Iscmaxr 45μA isc(t) Amp tB tE Time (ns) 1 0 ELEC 5970-003/6970-003

  9. Peak Short Circuit Current • Increases with the size (or gain, β) of transistors • Decreases with load capacitance, CL • Largest when CL= 0 • Reference: M. A. Ortega and J. Figueras, “Short Circuit Power Modeling in Submicron CMOS,” PATMOS’96, Aug. 1996, pp. 147-166. ELEC 5970-003/6970-003

  10. Short-Circuit Energy per Transition • Escr=∫tBtE VDD isc(t)dt = (tE – tB) IscmaxrVDD/2 • Escr = tr (VDD+ VTp-VTn) Iscmaxr/2 • Escf = tf (VDD+ VTp-VTn) Iscmaxf/2 • Escf = 0, when VDD = |VTp| + VTn ELEC 5970-003/6970-003

  11. Short-Circuit Energy • Increases with rise and fall times of input • Decreases for larger output load capacitance • Decreases and eventually becomes zero when VDD is scaled down but the threshold voltages are not scaled down ELEC 5970-003/6970-003

  12. Short-Circuit Power Calculation • Assume equal rise and fall times • Model input-output capacitive coupling (Miller capacitance) • Use a spice model for transistors • T. Sakurai and A. Newton, “Alpha-power Law MOSFET model and Its Application to a CMOS Inverter,” IEEE J. Solid State Circuits, vol. 25, April 1990, pp. 584-594. ELEC 5970-003/6970-003

  13. Pscvs. C 0.7μ CMOS 45% 3ns Input rise time Psc/Ptotal 0.5ns 0% 35 75 C (fF) ELEC 5970-003/6970-003

  14. Technology Scaling • Scale down by factors of 2 and 4, i.e., model 0.7, 0.35 and 0.17 micron technologies • Constant electric field assumed • Capacitance scaled down by the technology scale down factor ELEC 5970-003/6970-003

  15. Technology Scaling Results L=0.17μ, C=10fF 70% L=0.35μ, C=20fF Psc/Ptotal 10% L=0.7μ, C=40fF 0% tr (ns) 0.4 1.6 ELEC 5970-003/6970-003

  16. Effects of Scaling Down • 1-16% short-circuit power at 0.7 micron • 4-37% at 0.35 micron • 12-60% at 0.17 micron • Reference: S. R. Vemuru and N. Steinberg, “Short Circuit Power Dissipation Estimation for CMOS Logic Gates,” IEEE Trans. on Circuits and Systems I, vol. 41, Nov. 1994, pp. 762-765. ELEC 5970-003/6970-003

  17. Summary: Short-Circuit Power • Short-circuit power is consumed by each transition (increases with input transition time). • Reduction requires that gate output transition should not be slower than the input transition (faster gates can consume more short-circuit power). • Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power. ELEC 5970-003/6970-003

  18. Components of Power • Dynamic • Signal transitions • Logic activity • Glitches • Short-circuit • Static • Leakage ELEC 5970-003/6970-003

  19. Leakage Power VDD IG Ground R n+ n+ Isub IPT ID IGIDL ELEC 5970-003/6970-003

  20. Leakage Current Components • Subthreshold conduction, Isub • Reverse bias pn junction conduction, ID • Gate induced drain leakage, IGIDL due to tunneling at the gate-drain overlap • Drain source punchthrough, IPT due to short channel and high drain-source voltage • Gate tunneling, IGthrough thin oxide ELEC 5970-003/6970-003

  21. Subthreshold Current Isub = μ0 Cox (W/L) Vt2 exp{(VGS-VTH)/nVt} μ0: carrier surface mobility Cox: gate oxide capacitance per unit area L: channel length W: gate width Vt = kT/q: thermal voltage n: a technology parameter ELEC 5970-003/6970-003

  22. IDSfor Short Channel Device Isub = μ0 Cox (W/L) Vt2 exp{(VGS-VTH+ηVDS)/nVt} VDS = drain to source voltage η: a proportionality factor ELEC 5970-003/6970-003

  23. Increased Subthreshold Leakage Scaled device Ic Log Isub 0 VTH’ VTH Gate voltage ELEC 5970-003/6970-003

  24. Summary: Leakage Power • Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power. • For a gate it is a small fraction of the total power; it can be significant for very large circuits. • Scaling down features requires lowering the threshold voltage, which increases leakage power; roughly doubles with each shrinking. • Multiple-threshold devices are used to reduce leakage power. ELEC 5970-003/6970-003

  25. Components of Power • Dynamic • Signal transitions • Logic activity • Glitches • Short-circuit • Static • Leakage ELEC 5970-003/6970-003

  26. Power of a Transition isc VDD Power = CLVDD2/2 + Psc R Vo Vi CL R Ground ELEC 5970-003/6970-003

  27. Dynamic Power • Each transition of a gate consumes CV2/2. • Methods of power saving: • Minimize load capacitances • Transistor sizing • Library-based gate selection • Reduce transitions • Logic design • Glitch reduction ELEC 5970-003/6970-003

  28. Glitch Power Reduction • Design a digital circuit for minimum transient energy consumption by eliminating hazards ELEC 5970-003/6970-003

  29. Theorem 1 • For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition ELEC 5970-003/6970-003

  30. Theorem 2 • Given that events occur at the input of a gate (inertial delay = d ) at times t1 < . . . < tn , the number of events at the gate output cannot exceed tn – t1 -------- d min ( n , 1 + ) tn - t1 time t1 t2 t3 tn ELEC 5970-003/6970-003

  31. Minimum Transient Design • Minimum transient energy condition for a Boolean gate: | ti - tj | < d Where ti and tj are arrival times of input events and d is the inertial delay of gate ELEC 5970-003/6970-003

  32. Balanced Delay Method • All input events arrive simultaneously • Overall circuit delay not increased • Delay buffers may have to be inserted 4? 1 1 1 1 1 3 1 1 1 1 1 ELEC 5970-003/6970-003

  33. Hazard Filter Method • Gate delay is made greater than maximum input path delay difference • No delay buffers needed (least transient energy) • Overall circuit delay may increase 1 1 1 2 1 1? 3? 2 1 1 1 1 ELEC 5970-003/6970-003

  34. Linear Program • Variables: gate and buffer delays • Objective: minimize number of buffers • Subject to: overall circuit delay • Subject to: minimum transient condition for multi-input gates • AMPL, MINOS 5.5 (Fourer, Gay and Kernighan) ELEC 5970-003/6970-003

  35. Variables: Full Adder add1b 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 0 0 1 0 1 0 0 ELEC 5970-003/6970-003

  36. Objective Function • Ideal: minimize the number of non-zero delay buffers • Actual: sum of buffer delays ELEC 5970-003/6970-003

  37. Specify Critical Path Delay 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 0 0 1 0 1 0 0 Sum of delays on critical path ≤ maxdel ELEC 5970-003/6970-003

  38. Multi-Input Gate Condition d1 0 d 1 1 d 0 0 1 0 1 0 0 d2 d d1 - d2 ≤ d d2 - d1 ≤ d ELEC 5970-003/6970-003

  39. AMPL Solution: maxdel = 6 1 2 1 1 1 1 1 2 1 2 2 ELEC 5970-003/6970-003

  40. AMPL Solution: maxdel = 7 3 1 1 1 1 1 2 2 1 2 ELEC 5970-003/6970-003

  41. AMPL Solution: maxdel ≥ 11 5 1 1 1 1 3 2 3 4 ELEC 5970-003/6970-003

  42. Power* with respect to Ref. No. of buf. Ref: model del. Ref: unit del. maxdel Peak Ave. Peak Ave. 2 1 0 0.60 0.56 0.52 0.89 0.85 0.80 0.60 0.56 0.52 0.90 0.86 0.81 6 7 ≥11 Power Estimates for add1b * Hsiao et al., ICCAD-97 ELEC 5970-003/6970-003

  43. Power Calculation in Spice V VDD Open at t = 0 Energy, E(t) Circuit Large C t Ground 1 1 E(t) = -- C VDD 2 - -- C V 2 ~ C VDD ( VDD - V ) 2 2 Ref.: M. Shoji, CMOS Digital Circuit Technology, Prentice Hall, 1988, p. 172. ELEC 5970-003/6970-003

  44. Power Dissipation of ALU4 1 micron CMOS, 57 gates, 14 PI, 8 PO 100 random vectors simulated in Spice 7 6 5 Original ALU delay ~ 3.5ns 4 Energy in nanojoules 3 Minimum energy ALU delay ~ 10ns 2 1 0 1.5 0.0 0.5 2.0 1.0 microseconds ELEC 5970-003/6970-003

  45. F0 Output of ALU4 Original ALU, delay = 7 units (~3.5ns) 5 0 Signal Amplitude, Volts Minimum energy ALU, delay = 21 units (~10ns) 5 0 120 0 40 160 80 nanoseconds ELEC 5970-003/6970-003

  46. References • E. Jacobs and M. Berkelaar, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC/IEEE Workshop on Circuits, Systems and Signal Processing, Nov. 1996, pp. 183-188; also Int. Workshop on Logic Synthesis, May 1997. • V. D. Agrawal, “Low-Power Design by Hazard Filtering,” Proc. 10th Int. Conf. VLSI Design, Jan. 1997, pp. 193-197. • V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method,” Proc. 12th Int. Conf. VLSI Design, Jan. 1999, pp. 434-439. • Last two papers are available at website http://www.eng.auburn.edu/~vagrawal ELEC 5970-003/6970-003

  47. A Limitation • Constraints are written by path enumeration. • Since number of paths in a circuit can be exponential in circuit size, the formulation is infeasible for large circuits. • Example: c880 has 6.96M constraints. ELEC 5970-003/6970-003

  48. Timing Window • Define two timing windowvariables per gate output: • ti Earliest time of signal transition at gate i. • Ti Latest time of signal transition at gate i. t1, T1 ti, Ti . . . i tn, Tn Ref: T. Raja, Master’s Thesis, Rutgers Univ., 2002 ELEC 5970-003/6970-003

  49. Linear Program • Gate variables d4 . . . d12 • Buffer Variables d15 . . . d29 • Corresponding window variables t4 . . . t29 and T4 . . . T29. ELEC 5970-003/6970-003

  50. Multiple-Input Gate Constraints For Gate 7: T7> T5 + d7; t7 < t5 + d7; d7 > T7 - t7; T7> T6 + d7; t7 < t6 + d7; ELEC 5970-003/6970-003

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