CORE Generator System

1. CORE Generator System

2. Objectives • Describe the differences between LogiCORE and AllianceCORE solutions • List two benefits of using cores in your designs • Create customized cores by using the CORE Generator GUI • Instantiate cores into your schematic or HDL design • Run behavioral simulation on a design containing cores After completing this module, you will be able to:

3. Outline • Introduction • Using the CORE Generator System • CORE Generator Design Flows • Summary

4. What are Cores? • A core is a ready-made function that you can instantiate into your design as a “black box” • Cores can range in complexity • Simple arithmetic operators, such as adders, accumulators, and multipliers • System-level building blocks, including filters, transforms, and memories • Specialized functions, such as bus interfaces, controllers, and microprocessors • Some cores can be customized

5. Benefits of Using Cores • Save design time • Cores are created by expert designers who have in-depth knowledge of Xilinx FPGA architecture • Guaranteed functionality saves time during simulation • Increase design performance • Cores that contain mapping and placement information have predictable performance that is constant over device size and utilization • The data sheet for each core provides performance expectations • Use timing constraints to achieve maximum performance

6. Types of Cores • LogiCORE • AllianceCORE • The CORE Generator  GUI lists the type of each core

7. LogiCORE Solutions • Typically customizable • Fully tested, documented, and supported by Xilinx • Many are pre-placed for predictable timing • Many are unlicensed and provided for free with the Xilinx software • More complex LogiCORE products are licensed • Support VHDL and Verilog flows with several EDA tools • Schematic flow support for Foundation, Mentor, and Innoveda for most cores

8. AllianceCORE Solutions • Point-solution cores • Typically not customizable (some HDL versions are customizable) • Sold and supported by Xilinx AllianceCORE partners • Partners may be contacted directly to provide customized cores • All cores optimized for Xilinx; some are pre-placed • Typically supplied as an EDIF netlist • Support VHDL and Verilog flows, some schematic

9. Sample Functions • AllianceCORE solutions • Peripherals • DMA controllers • Programmable interrupt controllers • UARTs • Communications and networking • ATM • Reed-Solomon encoders / decoders • T1 framers • Standard bus interfaces • PCMCIA, USB • LogiCORE solutions • DSP functions • Time skew buffers, FIR filters, correlators • Math functions • Accumulators, adders, multipliers, integrators, square root • Memories • Pipelined delay elements, single and dual-port RAM • Synchronous FIFOs • PCI master and slave interfaces, PCI bridge

10. Outline • Introduction • Using the CORE Generator System • CORE Generator Design Flows • Summary

11. What is the CORE Generator System? • Graphical User Interface (GUI) that allows central access to the cores themselves, plus: • Data sheets • Customizable parameters (available for some cores) • Interfaces with design entry tools • Creates graphical symbols for schematic-based designs • Creates instantiation templates for HDL-based designs • Web access from the Help menu • The IP Center contains new cores to download and install • You always have access to the latest cores • Direct access to http://support.xilinx.com

12. Invoking the CORE Generator System • From the Project Navigator, select Project  New Source • Select IP (CoreGen & Architecture Wizard) and enter a filename • Click Next, then select the type of core

13. Xilinx CORE Generator System GUI Cores can be organized by function, vendor, or device family Core type, version, device support, vendor, and status

14. Selecting a Core • Double-click folders to browse the catalog of cores • Double-click a core to open its information window • Or select a core, and click the Customize or Data Sheet icons in the toolbar

15. Core Customize Window Core Overview tab provides version information and a brief functional description Parameters tab allows you to customize the core Web Links tab provides direct access to related Web pages Contact tab provides information about the vendor Data sheet access

16. CORE Data Sheets • Performance expectations (not shown) Features Functionality Pinout Resource utilization

17. Outline • Introduction • Using the CORE Generator System • CORE Generator Design Flows • Summary

18. Simulate Instantiate Implement Schematic Design Flow • Generate a core • Use the Edit  Project Options to select a schematic symbol instead of HDL templates • Creates an EDIF file and schematic symbol • Instantiate symbol onto your schematic • Treated as a “black box” - no underlying schematic • Proceed with normal schematic flow .EDN & Generate Core symbol .xco

19. compxlib.exe XilinxCoreLib Generate Core Instantiate Implement Simulate HDL Design Flow Compile library for behavioral simulation (one time only) .EDN Core generation and integration .VHD, .V .xco .VHO, .VEO

20. HDL Design Flow: Compile Simulation Library • Before your first behavioral simulation, you must run compxlib.exe to compile the XilinxCoreLib simulation library • Located in $XILINX\bin\<platform> • Supports ModelSim, Cadence NC-Verilog, VCS, Speedwave, and Scirocco • If you download new or updated cores, additional simulation models will be automatically extracted during installation

21. HDL Design Flow: Core Generation and Integration • Generate or purchase a core • Netlist file (EDN) • Instantiation template files (VHO or VEO) • Behavioral simulation wrapper files (VHD or V) • Instantiate the core into your HDL source • Cut and paste from the templates provided in the VEO or VHO file • Design is ready for synthesis and implementation • Use the wrapper files for behavioral simulation • ISE automatically uses wrapper files when cores are present in the design • VHDL: Analyze the wrapper file for each core before analyzing the file that instantiates the core

22. Outline • Introduction • Using the CORE Generator System • CORE Generator Design Flows • Summary

23. Review Questions • What is the main difference between the LogiCORE and the AllianceCORE products? • What is the purpose of compxlib.exe? • What is the difference between the VHO/VEO files and the VHD/V files that are created by the CORE Generator™ system?

24. Answers • What is the main difference between the LogiCORE and the AllianceCORE products? • LogiCORE products are sold and supported by Xilinx • AllianceCORE products are sold and supported by AllianceCORE partners • What is the purpose of compxlib.exe? • Makes it easy to compile the XilinxCoreLib library before your first behavioral simulation • What is the difference between the VHO/VEO files and the VHD/V files that are created by the CORE Generator™ system? • VHO/VEO files contain instantiation templates • VHD/V files are wrappers for behavioral simulation that reference the XilinxCoreLib library

25. Summary • A core is a ready-made function that you can “drop” into your design • LogiCORE  products are sold and supported by Xilinx • AllianceCORE  products are sold and supported by AllianceCORE partners • Using cores can save design time and provide increased performance • Cores can be used in schematic or HDL design flows

26. Where Can I Learn More? • Xilinx IP Center http://www.xilinx.com/ipcenter • Software updates • Download new cores as they are released • Tech Tips on http://support.xilinx.com • Software manuals: CORE Generator Guide