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LETI MODERN Contribution to WP5

LETI MODERN Contribution to WP5. Contribution to WP5.2 : Demonstrator : design, implementation and characterization Status : Design of a full chip in 32 nm : LoCoMoTIV Full AVFS architecture Including WP3 and WP4 IP contributions PG tape : December Deliverables:

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LETI MODERN Contribution to WP5

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  1. LETI MODERN Contribution to WP5 • Contribution to WP5.2: Demonstrator : design, implementation and characterization • Status : • Design of a full chip in 32 nm : LoCoMoTIV • Full AVFS architecture • Including WP3 and WP4 IP contributions • PG tape : December • Deliverables: • D5.2.2: Test chip simulation results : on track • D5.2.3 : IP block design and layout : on track • D5.5.4 : test chip characterization : on track

  2. A dynamic adaptive Architecture DVFS AVFS Power (mW) Period (ns) Same Speed Power supply (V) Same Power • Performances improvements: DVFS vs AVFS

  3. Architecture Overview A fine grainLocalDynamicAdaptive voltage and frequency scaling architecture Diagnostic: Process-Voltage-Temperature Timing fault detection or prevention (WP3) Actuators: Based on Vdd-hopping Local clock generation using FLL Power/Variability Control Local control with minimum hardware (WP4) Global control : high level algorithms RunTime 0.9v 0.9v 0.7v 0.7v ANOC CVPU PE CVPU PE Main HW objective : a minimum hardware based on standard cellsand simple analog macros for flow insertion and maximum efficiency

  4. LoCoMoTIV architecture An AVFS GALS approach at fine grain to reach an optimum energetic point according to PVT variations CVP-U NI NI NI CVP-U NI NI NI NI 16KB P-$ 16KB P-$ 16KB P-$ 16KB P-$ 32-KB TCDM 32-KB TCDM 32-KB TCDM 32-KB TCDM STxP70-V4(Rev. A) + ITC #1 STxP70-V4(Rev. A) + ITC #2 STxP70 STxP70 OCE OCE OCE OCE Local Compensation of Modern Technology Induced Variability Asynchronous NoC ITs ITs L2-RAM DMA WDT 4 XP70 µP 4 XP70 µP 4 XP70 µP 4 XP70 µP HWS S M M Dedicated memory blocks ANOC NI Memory Mapped Peripherals V/F Local actuators Timing Fault Detectors PVT sensors Hopping / FLL Hopping / FLL D-$ S PVT S PVT Local Controller CVP : Clock-Vraiability-Power Debug & Test Unit TMS TCK TDI TDO BI BO TMS TCK TDI TDO BI BO TMS TCK TDI TDO BI BO TMS TCK TDI TDO BI BO

  5. LoCoMoTIV flooplan BACK Hopping transition and switches : Voltage genration Fully digital FLL : Frequency generation PVT probes PE1 PE0 L2RAM ANOC PE3 PE2 CDMA

  6. Task 5.2 IFXA  Objective and Outline • Objective: development and verification of monitor & control (M&C) strategies for AMS&RF circuits to deal with aging/reliability issues and aging induced parameter variations in nanometer CMOS. • Close link to T3.3 (M&C concept development) • Outline • Basic aging/reliability assessment  identify sensitivities • Aging simulations (proof of sim.-concept, model-hardware correlation in T5.2) • Dedicated test-structures for transient effects and aging-parameter-variations • Development of M&C concepts  T3.3 • Implementation and verification of M&C concepts • Silicon based proof of concept • Concept development for accelerated aging/stress tests  T5.2 • Development of characterization methods (fast transient effects)  T5.2 MODERN General Meetings Catania, Nov. 9 & 10, 2010

  7. Task 5.2 IFXA  Completed and Remaining Activities • Test-chip status: • TC #1 (32nm CMOS): taped, lab characterization completed • TC #2 (32nm CMOS): taped, lab characterization on-going • TC #3 (28nm CMOS): design on-going, tape-out end 2010 • Status basic aging/reliability assessment (-> circuit level results) • Circuit level aging simulation flow proven on TC1 (OpAmps, VCOs) • Structures for transient effects and aging-variations implemented on TC2 • VCO: aging of startup VDD • OpAmp: Offset drift • Static offset • Recovery MODERN General Meetings Catania, Nov. 9 & 10, 2010

  8. BACK Task 5.2 IFXA  Completed and Remaining Activities • Status implementation & verification of M&C concepts • Accelerated aging test-setup proven on TC1 and TC2 (OpAmps, VCOs) • Fast offset characterization method (transient effects) proven on TC2 • Measurements to be finalized on TC2 • ADC incl. error correction (static & transient offsets) • Switch degradation monitor circuits • Variations of aging parameters • Novel burn-in concept (to increase robustness and compensate PV) • Macros to be implemented on TC3 • Switch control circuits to be implemented on TC3 • DCDC test-structures MODERN General Meetings Catania, Nov. 9 & 10, 2010

  9. Task 3.3 IFXA  Key Results Aging Assessment • Majority of key blocks AMS & RF is inherently robust (“self-regulation”) • Sensitive cases • Non-linear / asymmetric operation (comparator) • Full scale driven devices (switches, VCO, …) • Transient effects (recovery) significantly contribute • Variations of aging parameters need to be considered ( T5.2) • Scaling 65nm to 32nm: not absolute values but sensitivities change • OpAmp: Offset drift • VCO: aging of startup VDD • Static offset • Recovery MODERN General Meetings Catania, Nov. 9 & 10, 2010

  10. Task 3.3 IFXA  Key Results M&C Development • Switches • Monitor concepts: ring oscillator, current sensing • Control: “frequency locked loop”, analog control loop • Aging induced offsets • Avoid offset generation: e.g. chopping (comparator) • Correction of static & dynamic effects: e.g. error correction by redundancy • Burn-in: dedicated stress to increase robustness and compensate PV ADC search algorithm incl. redundancy MODERN General Meetings Catania, Nov. 9 & 10, 2010

  11. Task 3.3 IFXA  Completed and Remaining Activities • Testchip #1 and #2 taped, samples not fully characterized, design of #3 on-going • Basic aging/reliability assessment  almost completed • Simulations completed, sim.-concept verified (TC1, OpAmps, VCOs) • Structures for transient effects and aging-variations implemented on TC2 • Development of M&C concepts  completed • Implementation and verification of M&C concepts  ongoing • Accelerated aging test-setup proven on TC1 and TC2 • Fast offset characterization method proven on TC2 • TC2 • Switch monitor circuits • ADC incl. error correction • TC3 • Switch control circuits to be implemented on TC3 • DCDC test-structures • Concept development for accelerated aging/stress tests MODERN General Meetings Catania, Nov. 9 & 10, 2010

  12. MODERN General Meetings Catania, Nov. 9 & 10, 2010

  13. MODERN General Meetings Catania, Nov. 9 & 10, 2010

  14. BACK MODERN General Meetings Catania, Nov. 9 & 10, 2010

  15. MODERN WP5 THALES foreseen activities 10 November 2010

  16. THL activities in MODERN linked to WP5 • Up to now we (THL) have had contributions in WP4 to develop a SystemC simulator of a predictable fault-tolerant multicore chip (based on the ISD network) with embedded middleware and operating libraries. • developed a processor tile • designed and implemented fault injection scenarios • design the multicore chip with ISD network • implemented a SystemC simulator of the chip • designed and implemented operating libraries, middleware and tools • modified in-house tools to generate parallel code for this architecture • designed, developed and implemented a video detection algorithm on top of the architecture based on the Viola & Jones face detection (Haar filters). WP4 Web Meeting

  17. TILE N Supervisor : TILE 0 TILE 1 CTR CTR ACC ACC CTR DMA DMA DMA LMEM LMEM LMEM NIM NIM NIM Architecture (SystemC) iNoC : Internal Network OCP TL2 … ISD HyperCube Network NUMA SHMEM • CTR: ConTRoler • DMA: Direct Memory Access • NIM: Network Interface Module • (Makes network protocol translation) ACC:ACCelerator LMEM:Local MEMory SHMEM:SHared MEMory NUMA: Non Uniform Memory Access WP4 Web Meeting

  18. Fault Scenario Definition • Memory faults: a fault occurs randomly in shared data memory (e.g. wrong value written). A read time, the memory tells the reading tile that data contains errors. This reading tile sends a message to the supervisor tile. The supervisor takes actions to solve the problem. • Tile faults: a processing tile sends periodically a message to the supervisor tile (watchdog). When it stops doing so, the supervisor takes actions to solve the problem. • To solve a problem, the supervisor : • Stops the processing tiles • Find a new memory mapping and tile mapping. • Configure the network according to that mapping. • Restart the processing tiles WP4 Web Meeting

  19. Supervisor : TILE 0 CTR DMA LMEM NIM BACK WP5 foreseen activities and deadlines • WP5: multicore chip FPGA implementation • M27: D5.2.2: • VHDL IPs developed • supervisor Tile, NIM, SHMEM controler, NoC • Software developed • Tile bootloader, SHMEM test access • M36: D5.3.3 • Several Tiles (12 foreseen) • Develop HAL • Reuse Operating Libraries from SystemC • Video detection application.

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