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Predictive Modeling of Lithography-Induced Linewidth Variation

Predictive Modeling of Lithography-Induced Linewidth Variation. Swamy V. Muddu University of California San Diego Photomask Japan 2008 (Presented by Kwangok Jeong). Sensitive to grow due to defocus. Sensitive to resist effects. Sensitive to exposure variation. Sensitive to shrink

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Predictive Modeling of Lithography-Induced Linewidth Variation

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  1. Predictive Modeling of Lithography-Induced Linewidth Variation Swamy V. Muddu University of California San Diego Photomask Japan 2008 (Presented by Kwangok Jeong)

  2. Sensitive to grow due to defocus Sensitive to resist effects Sensitive to exposure variation Sensitive to shrink due to defocus Modeling Litho-Induced Linewidth (CD) Variation • Device layout geometries are no longer regular • Design needs litho-simulated layout shapes • Device performance/leakage depend on the device contour •  Contour of device needed for driving accurate design in sub-45nm technologies • Sources of lithography-induced systematic critical dimension (CD) variation • Defocus, exposure dose, topography, mask errors, overlay etc. • Simulation of litho processes on layout  computationally very expensive Image source: Andrez Strojwas, ASPDAC06

  3. Device CD Topography Defocus Mask Error Exposure Modeling Litho-Induced CD Variability • Goal: Modeling systematic variation of CD caused during lithography by accurately characterizing impact of variation sources on representative layout patterns • Use model: drive litho-aware design analysis and optimization without OPC and litho simulation •  during iterative “litho-aware” layout optimizations (e.g., detailed placement / detailed routing with knowledge of litho impact) •  fast, chip-level analysis of post-litho device dimensions and its performance impact Layout patterns representative of technology OPC / lithography simulation Linewidth (CD)model Regression/Response Surface Modeling

  4. Legend: Drawn poly Diffusion Litho contour Gate poly Modeling Device CD • Performance (on-current = Ion) and power (leakage/off-current = Ioff) depend on the device CD •  the main region of interest in polysilicon is the “gate poly” • Our work: model CD from litho contour of gate poly Snapshot of a layout in 65nm technologyshowing the deviation in litho contour fromthe drawn layout at worst defocus

  5. Device EPE Topography Defocus Mask Error Exposure Modeling CD  Modeling Edge Placement Error • EPE: deviation of litho contour from device “edge” •  provides reference to the drawn device unlike CD • Construct model of device EPE variation with focus/exposure dose  predict device EPE at design level Focus (F) and exposure dose (E) are the main contributors. Other sources of variation can be translated to F/E variation Device EPE is not constant along device width  sample EPE at multiple locations and capture their layout dependence

  6. Predictive EPE Modeling Methodology Full-Chip Layout (poly and diffusion) Layout Parameter Space Modeling Prediction Parameter Screening (parameter reduction) Device LayoutAnalysis Exhaustive DOE (w/ reduced parameter set) Device GeometricParameters OPC and LithoSim(process window (PW)) Mapping to DOE Configurations Response SurfaceModeling Predictive Model of Device EPE EPE Prediction Device EPE (at multiple locations) End goal: |EPE delta| < 2nm

  7. Capturing Layout Parameters • Layout geometry shapes determine litho contour across PW • Capturing device layout parameters important for model construction • Ground rules for abstracting layout shapes using parameters • A shape can be defined by a sequence of points in x-y plane. The sequence can be clockwise or anti-clockwise • Any two consecutive points in the shape arraydefine an edge • Any polygon edge can take four possible directions – right, left, top or bottom Basic device layout inManhattan geometryshowing device body, top and bottom terminations Representation ofdevice geometry with points and edges

  8. Capturing Layout Parameters – Device Classification • Any two isolated devices in the layout differ only in their top and bottom terminations  classify devices on this basis • Top or bottom termination can be of three types • Line end (E) • Line corner (C) • Line taper (T) • Total number of possible device configurations = 36 • Line end definition • If point-after-P2 == point-before P3, then termination = line end • Layout parameter of line end • Line end extension (LEE): Spacing between gate poly boundary and termination of line end

  9. Device Classification – Line Corner • Line corner definition • If point-after P2 and point-before P3 are on the same side of the device segments (P1P2 and P3P4 respectively), then the termination is a corner • A corner can be oriented left or right (LC or RC) • Layout parameter of line corner • Left Corner Spacing (LCS): Spacing between gate poly boundary and left edge BP3P3 • Left Corner Extent (LCS): Length of the edge BP3P3 • Right Corner Spacing (RCS): Spacing between gate poly boundary and right edge P2AP2 • Right Corner Extent (RCE): Length of the edge P2AP2 • Similar definitions apply for right corner • Left and right corner definitions apply for bottom termination also

  10. Device Classification – Line Taper • Line taper definition • If point-after P2 and point-before P3 are on the different sides of the device segments (P1P2 and P3P4 respectively), then the termination is a taper • Depending on the spacing between gate poly boundary and segments BP3P3 and P2AP2, a taper can be • Left-proximal (left edge closer to boundary) – LT • Right-proximal (right edge closer to boundary) – RT • Uniform (left and right edges are at uniform distance) – UT • Layout parameter of line taper • Left Taper Spacing (LTS): Spacing between gate poly boundary and left edge BP3P3 • Left Taper Extent (LTE): Length of the edge BP3P3 • Right Taper Spacing (RTS): Spacing between gate poly boundary and right edge P2AP2 • Right Taper Extent (RTE): Length of the edge P2AP2 • Similar definitions apply for right corner • Left and right corner definitions apply for bottom termination also

  11. Capturing Layout Parameters – Neighbor Interactions • The geometry of field poly surrounding a device affects its contour  optical interactions • Capturing neighbor interactions: 1D and 2D poly in the edge interaction region of a device • Number of layout parameters representing a device configuration (including those of neighbor poly) ~ 20 • Infeasible even for a modest 3-level design of experiments  reduce dimensionality of layout parameter space 1D neighbor poly:Constituted of vertical field poly shapes only 2D neighbor poly:Constituted of vertical and horizontal field poly shapes onlyThe figure shows a convex corner

  12. Pruning Layout Parameter Space • We utilize observations of litho contour variation to filter out unimportant layout parameters • Observations: • #1: Poly geometries outside the edge interaction region do not affect device contour • #2: Only convex corners of neighbor poly affect device contour • #3: Corners of neighbor poly beyond the first neighbor do not affect device contour • #4: Beyond the first neighbor, poly affect the device contour only if their normals coincide • Observations above corroborated with experimental data generated from litho simulation across the process window • Number of layout parameters reduced from ~20 to ~10 (depending on the device configuration)

  13. Design of Experiments (DOE) for Modeling • DOE is a well-studied topic in industrial process optimization • “Optimal” DOE exist for 2-level / 3-level, multi-factor experiments • Study first and second-order dependencies between inputs/outputs • Proposed setup: multi-level, multi-factor  no optimal designs • Factors: layout parameters • Levels: samples from the distribution of layout parameters • For EPE modeling, create DOE for each of the 36 device configurations • Values of layout parameters in each configuration obtained from sampling of parameter distributions • Sampling criterion: • Any sampling of parameter distribution must include the peaks • Include samples from the regions of the distribution that contribute to most of the variation in output • Utilize the knowledge of the trend in response w.r.t. a parameter during sampling

  14. Layout Parameter Distributions • Distribution of device widths taken from a 65nm industrial benchmark with ~1M devices

  15. Layout Parameter Distributions (contd.) • Distribution of line end extension (LEE) parameter of devices in a 65nm industrial benchmark

  16. Layout Parameter Distributions (contd.) • Distribution of spacing to left corners in the top termination of devices in a 65nm industrial benchmark

  17. EPE Modeling • To generate EPE data for modeling, create a DOE for each device configuration • Perform OPC and litho simulation across process window (i.e., different defocus X exposure conditions) and extract device EPE at multiple locations • Bottom, first-quarter (25% of width), center, third-quarter (75% of width) and top EPE of the device • Analyze EPE at each location w.r.t. each parameter EPE variation with LCS EPE variation with Defocus EPE variation with ExposureDose

  18. EPE Modeling – Model Selection • One dimensional analysis not sufficient to capture interactions between parameters • Use response surface analysis to guide multi-dimensional fitting • EPE response with each dimension can be modeled with a low-order polynomial • Linear regression can be used for fitting (function is linear in the unknown parameters of the model) View of multi-dimensional data set in rstool (MATLAB) EPE variation across 6 layout and 2 litho dimensions

  19. Experimental Methodology • Layout parameter extraction • To generate parameter distributions for sampling • Performed using GDSII shape analysis routines (OpenAccess) • Parameter sampling and DOE construction • Parameters obtained from sampling distributions • DOE generated using scripted interfaces to Mentor Calibre • OPC and process window lithography simulation • OPC recipes in 90nm and 65nm optimized for minimum (~0nm) EPE variation at nominal process conditions • Defocus optical models generated for litho simulation • Data analysis and regression • EPE data obtained from analysis of device contours in DOE • Response surface analysis performed in MATLAB • Linear regression performed with R (statistical analysis tool)

  20. Experimental Methodology (contd.) • Experiments performed with TSMC 90nm and 65nm layouts • Process window litho simulation • 90nm – 27 defocus, exposure dose conditions • Defocus range: (-100nm, +100nm), dose range: (-3%, +3%) • 65nm – 21 defocus, exposure dose conditions • Defocus range: (-75nm, +75nm), dose range: (-4%, +4%) Number of DOE configurations for model generation (Config representation = top, bottom termination) OPC / Litho model parameters

  21. Modeling Results • EPE model fit based on the analysis of response surface • Quality of fit evaluated with R2 (coefficient of determination), root mean-squared error (RMSE) and residual plots • Fit improved until RMSE < 1nm Results of linear regression for bottom, first quarter (25% of width), center, third quarter (75% of width), top EPE of left (_l) and right (_r) device edges in 90nm technology

  22. EPE Prediction – Scatter Plot • EPE models used for prediction at the chip layout level in 90/65nm technologies • Testcases: c432, c880, c3540 with 710, 1152 and 3464 devices • Predicted EPE compared with actual EPE across the process window 90nm c432: Distribution of prediction error Mean: -0.11nm 95% of errors within 1.6nm 90nm c432: Scatter plot of actual versus predicted EPE at 145923 data points

  23. EPE Prediction Results Statistics of the discrepancy between actual EPE and predicted EPE in 90nm and 65nm technologies

  24. Conclusions • Drivers for predictive modeling approach are: • Fast, chip-level analysis of post-litho layout dimensions • Use in iterative layout optimizations (without the need for incremental litho simulations) • Proposed predictive model cannot replacea sign-off quality litho simulator, but is a fast approximation • EPE prediction error (i.e., EPEactual – EPEpredicted) is spread within (-3nm,+3nm) with  ~ 1nm •  70% of prediction errors < 1nm • This accuracy is acceptable during fast layout analysis / iterative “litho-aware” optimizations

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