DRRA Dynamically Reconfigurable Resource Array

1. DRRADynamically Reconfigurable Resource Array Ahmed Hemani Dept. Of ES, School of ICT, KTH Kista Email: hemani@kth.se Website: www.it.kth.se/~hemani

2. DRRA Dynamically Reconfigurable Resource Array • ASIC like arbitrary parallelism, local and hierarchical control • Software like flexibility • Regular, seamless topology • Easy mapping • Perfect energy and performance prediction • Full custom will compensate the reconfiguration overheads • Private execution environments • Minimal movement of data • Move Logic Not Data • Vectorising, Symbolic Assembler under development • C/Matlab compiler to be developed

3. DRRA System Concept Runtime Management System Power Management External IF Manager Resource Manager Application Manager Private execution environments for three applications . . . Application 1 Application 3 Application 2 + + + + + + + + + + + + Reconfigurable Arithmetic Resource Pool External Data Exchange Interconnect Applications run concurrently in their private execution environments in DRRA Protocol Processor Pool . . . Application Controller (SW) Application Processor - RISC . . . Protocol Processing Layers Controller (SW+CW) 3D Distributed Memory Pool Physical Layer Controllers (HW) Modem/Codec etc. Controller Run Time Management System Processor -RISC . . . Register File Pool Rx/Decode etc. Ctrlr Tx/Encode etc. Ctrlr . . . Algorithm Datapath Algorithm Datapath Algorithm Datapath Reconfigurable Control Logic Resource Pool look at http://web.it.kth.se/~hemani/DRRA%20Summary.pdf 3. DRRA System Architecture Control and Configuration Interconnect

4. DRRA PHY Layer Fabric 12 16b buses 7 X 2 16b buses Regiser File 16b X 64 2 Read , 2 Write Ports Burst Mode, Shift and Circular Buffer Mode Addrs Gen. Unit Context Memory Morphable DPU 16 bit, 32 bit accumulator 4 Inputs, 2 Outputs MAC, Butterfly, 5 stage pipeline ADD/SUB tree Sum of Difference, Difference of Sum LFSR, Counter, Comparators Windowed Truncation, Saturation Context Memory Sequencer Simple sequential flow Conditional and Counter based Loop and branching Controls Register File, mDPU and Interconnect switches Interconnect 3 hop, Sliding window Fully connected Segmented 7 hop Wires Circuit Switchd Network Local Config Memory Fabric Scalabe, Regular Topology Interfaces to Distributed Memory and Central Controller

5. Initial Results Layout of 7X2 mDPUs, Regfiles and Sequencers, Corresponding to the fabric shown on the previous slide 90 nm, 720 MHz 11 tap FIR– Symmetric ~300 pJ, ~6 ns. Unoptimised N.B. 1 mDPU and 1 Regfile used 90 nm, 720 MHz 64 point FFT – radix -2 DIT ~50 nJ, ~300 ns. Unoptimised N.B. 4 mDPUs and 4 Regfiles used Long term goal is to come very close to ASIC with full custom datapath

6. Vectorising Symbolic Assembler N is the order of the filter. M is the degree of parallelism All serial parallel solutions are concisely captured by this pattern

7. The mapping for N=101, M = 7 refi_0_0 refi_0_1 refi_0_2 refi_0_3 refi_0_4 refi_0_5 refi_0_6 newSample x100 x93 x86 x79 x72 x65 x57 x0 x7 x14 x21 x28 x35 x43 x94 x87 x80 x73 x66 x6 x13 x20 x27 x34 x49 x51 x58 x42 x50 refi_1_1 refi_1_0 refi_1_2 refi_1_3 refi_1_4 refi_1_5 refi_1_6 C7-C13 C14-C20 C21-C27 C43-C50 C28-C34 C35-C42 C0-C6 + + + + + + × × × × × × × + + + + + + + + p0 p1 p2 p3 p4 p5 p6 adderTree4 0 + + + + + + 0 0 + + + convSum

8. Protocol Processor Concept API To Higher Layer Constants Error Chk Encryp/ Decryp Memory Frag / Defrag Bit Field Analysis Control and Timing Registers API To Lower Layer For explaination look at http://web.it.kth.se/~hemani/DRRA%20Summary.pdf Go to section 5: Protocol Processor Architecture

9. REXAPPRadio Experimentation & Prototyping Platform Configurable RF/Analog Impairment Models Control, Configuration, Debug and Monitoring RF/Analog Rx Baseband Rx Protocol Processing Layers Application Layer RF/Analog Tx Baseband Tx High Capacity, High Bandwidth Storage Configurable Chanel Model Host Interface RF/Analog Rx Baseband Rx Protocol Processing Layers Application Layer RF/Analog Tx Baseband Tx Control, Configuration, Debug and Monitoring Resources

10. Vision for the future RF/Analog/Sensors/peripherals Logic Tile - Giga Gates Volatile Memory - GigaBytes Non-Volatile Memory - TeraBytes Don’t stop dreaming !