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Optimizations for Faster Simulation of Esterel Programs

Explore advancements in optimizing Esterel programs for faster simulation. Investigate compilation trends, semantical issues, and efficient simulation methods. Thesis defense on November 26, 2002, in Agelonde, France.

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Optimizations for Faster Simulation of Esterel Programs

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  1. Optimizations for Faster Simulation of Esterel Programs Dumitru POTOP-BUTUCARU Advisers: Gérard Berry – Esterel Technologies Robert de Simone – INRIA, project TICK PhD Thesis Defense, 26 November 2002, Agelonde, France

  2. Part 1: Why? • Background • Motivation Part 2: How? • Presentation of the work • Results and conclusion

  3. Two compilation trends • Semantic completeness • Formal semantics (Esterel v5) • Formal models (automata, circuits) • Formal analysis and optimization methods • Efficiency issues (do not scale up well) • Efficient simulation • Custom intermediate formats • Scale up well • Semantic issues

  4. Why? Because of Esterel properties if(BOOT){A_active=1;B_active=1;} else { if(R){A_active=1;B_active=1;} else if(A_active|B_active) { if(A_active) if(A) {A_active=0;B=1;} if(B_active) if(B) B_active=0; if(!(A_active|B_active)) O=1; } } • Structural imperative style loop [ await A;emit B || await B ]; emit O; halt every R • Esterel source = control-flow specification • well-structured code • control-flow optimizations • But…

  5. Why? Because of Esterel properties • Constructive causality • Correct causality cycles • Instantaneous reaction to signal absence (analysis of not yet executed code) • Solution: Translate into a formal mathematical model • But: Loss of efficiency causality cycle signal S,T in emit S; present T then present S else emit T end end; end break the cycle

  6. Current methods Semantically complete Efficient code Intermediate model Explicit FSM Circuits ? Expensive, slow General Cheap, fast General* Cheap, fast Only “acyclic” programs Compiling method Bisimulation (fc2tools) RTL optimizations (SIS) Classical control-flow optimizations Optimization Generated code (without optim.) Very large, Very fast Small Slow Very small Very fast Semantics (acyclic=?) Less powerful optim. Problems Do not scale up well *=sccausalorslow simulation

  7. What we want • Generate efficient code for “good” programs • Generate code for all programs • Understand cyclicity at a higher level • Inexpensive optimizations based on static analysis • Formalize the efficient approach • New intermediate format/model (GRC) • Hierarchical state representation • Control-flow graph • No specific encoding Means

  8. Part II - Outline • The GRC format • Definition (small example) • Code generation for “acyclic” GRC specifications • State encoding • Scheduling • Static analysis for optimizations • Cyclic specifications • What “cyclic” means? • Implementation and benchmarks • Conclusion

  9. GRC format – a small example 1 boot: loop [ await A;emit B || await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # loop-every halt 6 enter4 exit 1 enter2 enter3 enter5 [1] exit2 0 Inactive[4] [2] R 4 exit4 emit B K0[4] exit3 enter6 K0 emit O A K1[4] K1 Inactive[5] [3] 5 exit5 K0[5] 2 B [6] K1[5]

  10. GRC format – a small example 1 boot: loop [ await A;emit B || await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # loop-every halt 6 selection tree = parallel/exclusive abstraction of the syntax tree The nodes represent the activation of various statements

  11. GRC format – a small example 1 boot: » loop [ await A;emit B || await B ]; emit O; halt every R 0 # Initial state 4 await A 3 || await B 2 5 # loop-every halt 6

  12. GRC format – a small example 1 boot: loop [ await A;emit B || await B ]; emit O; halt every R 0 # After the first reaction – waiting for A and B 4 await A 3 || await B 2 5 # loop-every halt 6

  13. GRC format – a small example 1 boot: loop [ await A;emit B || await B ]; emit O; halt every R 0 # B has been received. Waiting for A 4 await A 3 || await B 2 5 # loop-every halt 6

  14. GRC format – a small example 1 boot: loop [ await A;emit B || await B ]; emit O; halt every R 0 # A has been received. Halted 4 await A 3 || await B 2 5 # loop-every halt 6

  15. GRC format – a small example 1 boot: loop [ await A;emit B || await B ]; emit O; halt every R 0 # Program reset after R has been received 4 await A 3 || await B 2 5 # loop-every halt 6

  16. GRC format – a small example 1 boot: loop [ await A;emit B || await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # loop-every halt 6 enter4 exit 1 enter2 enter3 enter5 [1] exit2 0 Inactive[4] [2] R 4 exit4 emit B K0[4] exit3 enter6 K0 emit O A K1[4] K1 Inactive[5] [3] 5 exit5 K0[5] 2 B [6] K1[5]

  17. GRC format – a small example 1 boot: • loop [ await A;emit B || await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # loop-every halt 6 enter4 exit 1 enter2 enter3 enter5 [1] exit2 0 Inactive[4] [2] • R 4 exit4 emit B K0[4] exit3 enter6 K0 emit O A K1[4] K1 Inactive[5] [3] 5 exit5 K0[5] 2 Rabsent, Apresent B [6] K1[5]

  18. GRC format – a small example 1 boot: •loop [ await A;emit B || await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # loop-every halt 6 enter4 exit 1 enter2 enter3 enter5 [1] exit2 0 Inactive[4] [2] R 4 exit4 emit B K0[4] exit3 enter6 K0 emit O • A K1[4] K1 Inactive[5] [3] 5 exit5 K0[5] 2 Rabsent, Apresent B [6] K1[5]

  19. GRC format – a small example 1 boot: loop [ await A;emit B •|| await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # loop-every halt 6 enter4 exit 1 enter2 enter3 enter5 [1] exit2 0 Inactive[4] [2] R 4 exit4 emit B K0[4] exit3 enter6 K0 emit O A K1[4] K1 • Inactive[5] [3] 5 exit5 K0[5] 2 Rabsent, Apresent B [6] K1[5]

  20. GRC format – a small example 1 boot: loop [ •await A;emit B || await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # loop-every halt 6 enter4 exit 1 enter2 enter3 enter5 [1] exit2 0 Inactive[4] [2] R 4 exit4 emit B K0[4] exit3 enter6 K0 emit O A • K1[4] K1 Inactive[5] [3] 5 exit5 K0[5] 2 Rabsent, Apresent B [6] K1[5]

  21. GRC format – a small example 1 boot: loop [ await A;emit B• || await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # loop-every halt 6 enter4 exit 1 enter2 enter3 enter5 [1] exit2 0 Inactive[4] [2] R 4 exit4 emit B K0[4] exit3 enter6 K0 emit O A K1[4] K1 Inactive[5] [3] 5 exit5 K0[5] 2 Rabsent, Apresent B [6] K1[5]

  22. GRC format – a small example 1 boot: loop [ await A;emit B || await B ]•; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # loop-every halt 6 enter4 exit 1 enter2 enter3 enter5 [1] exit2 0 Inactive[4] [2] • R 4 exit4 emit B K0[4] exit3 enter6 K0 emit O A K1[4] K1 Inactive[5] [3] 5 exit5 K0[5] 2 Rabsent, Apresent B [6] K1[5]

  23. GRC format – a small example 1 boot: loop [ await A;emit B || await B ]; •emit O; halt every R 0 # 4 await A 3 || await B 2 5 # loop-every halt 6 enter4 exit 1 enter2 enter3 enter5 [1] exit2 0 Inactive[4] [2] • R 4 exit4 emit B K0[4] exit3 enter6 K0 emit O A K1[4] K1 Inactive[5] [3] 5 exit5 K0[5] 2 Rabsent, Apresent B [6] K1[5]

  24. GRC format – a small example 1 boot: loop [ await A;emit B || await B ]; emit O; •halt every R 0 # 4 await A 3 || await B 2 5 # loop-every halt 6 enter4 exit 1 enter2 enter3 enter5 [1] exit2 0 Inactive[4] [2] • R 4 exit4 emit B K0[4] exit3 enter6 K0 emit O A K1[4] K1 Inactive[5] [3] 5 exit5 K0[5] 2 Rabsent, Apresent B [6] K1[5]

  25. GRC format – a small example 1 boot: loop [ await A;emit B || await B ]; emit O; halt every R 0 # 4 await A 3 || await B 2 5 # loop-every halt 6 enter4 exit 1 enter2 enter3 enter5 [1] exit2 0 Inactive[4] [2] R 4 exit4 emit B K0[4] exit3 enter6 K0 emit O A K1[4] K1 Inactive[5] [3] 5 exit5 K0[5] 2 Rabsent, Apresent B [6] K1[5]

  26. Code generation – acyclic case • “Good programs” => acyclic GRC flowgraphs • Code generation for acyclic specifications • State encoding • Software-specific • Bitwise • Hierarchic • Static scheduling • Respects the causality

  27. Code generation – acyclic case boot: 0 # • State encoding 1 await A || await B 0 # 1 loop-every halt Bit index: States: – boot instant – « await A » active, « await B » completed – « await A » active, « await B » active – « halt » active – program terminated

  28. Code generation – acyclic case 1 boot: 0 0 # 4 1 await A 3 • State encoding || await B 0 5 2 # 1 loop-every halt 6 enter4 exit 1 enter2 enter3 enter5 exit2 [1] Inactive[4] 0 [2] 4 R exit4 emit B K0[4] exit3 enter6 K0 emit O A K1[4] K1 Inactive[5] [3] 2 5 exit5 K0[5] [6] B K1[5]

  29. Code generation – acyclic case 1 boot: 0 0 # 4 1 await A 3 • State encoding || await B 0 5 2 # 1 loop-every halt 6 enter4 exit 1 enter2 enter3 enter5 exit2 Inactive[4] S[1] 4 R exit4 emit B K0[4] exit3 enter6 K0 emit O A K1[4] K1 Inactive[5] S[2] 5 exit5 K0[5] B K1[5]

  30. Code generation – acyclic case 1 boot: 0 0 # 4 1 await A 3 • State encoding || await B 0 5 2 # 1 loop-every halt 6 enter 4 exit 1 enter 2 enter 3 enter 5 exit2 Inactive[4] S[1] S[3] R exit4 emit B K0[4] exit3 enter 6 K0 emit O A K1[4] K1 Inactive[5] S[2] S[4] exit5 K0[5] B K1[5]

  31. Code generation – acyclic case 1 boot: 0 0 # 4 1 await A 3 • State encoding || await B 0 5 2 # 1 loop-every halt 6 S[3]=1 exit 1 S[1]=1 S[2]=0 S[4]=1 exit2 Inactive[4] S[1] S[3] R exit4 emit B K0[4] exit3 S[2]=1 K0 emit O A K1[4] K1 Inactive[5] S[2] S[4] exit5 K0[5] B K1[5]

  32. Code generation – acyclic case 1 boot: 0 0 # 4 1 await A 3 • State encoding || await B 0 5 2 # 1 loop-every halt 6 S[3]=1 S[1]=1 S[2]=0 S[4]=1 Inactive[4] S[1] S[3] R S[3]=0 emit B K0[4] S[2]=1 K0 emit O A K1[4] K1 Inactive[5] S[2] S[4] S[4]=0 K0[5] B K1[5]

  33. Code generation – acyclic case 1 boot: 0 0 # 4 1 await A 3 • State encoding || await B 0 5 2 # 1 loop-every halt 6 S[3]=1 S[1]=1 S[2]=0 S[4]=1 Inactive[4] S[1] S[3] R S[3]=0 emit B K0[4] S[2]=1 K0 emit O A K1[4] K1 Inactive[5] S[2] S[4] S[4]=0 K0[5] B K1[5]

  34. Code generation – acyclic case 1 boot: 0 0 # 4 1 await A 3 • State encoding || await B 0 5 2 # 1 loop-every halt 6 S[1..4]=1011 Inactive[4] S[1] S[3] R S[3]=0 emit B K0[4] K0 emit O S[2]=1 A K1[4] K1 Inactive[5] S[2] S[4] S[4]=0 K0[5] B K1[5]

  35. Code generation – acyclic case • Static scheduling if(S[1]){ } else { } S[1..4]=1011 Inactive[4] S[1] S[3] R S[3]=0 emit B K0[4] K0 emit O S[2]=1 A K1[4] K1 Inactive[5] S[2] S[4] S[4]=0 K0[5] B K1[5]

  36. Code generation – acyclic case • Static scheduling if(S[1]){ if(R){ } else { } } else { } S[1..4]=1011 Inactive[4] S[1] S[3] R S[3]=0 emit B K0[4] K0 emit O S[2]=1 A K1[4] K1 Inactive[5] S[2] S[4] S[4]=0 K0[5] B K1[5]

  37. Code generation – acyclic case • Static scheduling bool aux=0; if(S[1]){ if(R){aux=1;} else { } } else {aux=1;} if(aux){ } S[1..4]=1011 Inactive[4] S[1] S[3] R S[3]=0 emit B K0[4] K0 emit O S[2]=1 A K1[4] K1 Inactive[5] S[2] S[4] S[4]=0 K0[5] B K1[5]

  38. Code generation – acyclic case • Static scheduling bool aux=0; if(S[1]){ if(R){aux=1;} else { } } else {aux=1;} if(aux){S[1..4]=1011;} S[1..4]=1011 Inactive[4] S[1] S[3] R S[3]=0 emit B K0[4] K0 emit O S[2]=1 A K1[4] K1 Inactive[5] S[2] S[4] S[4]=0 K0[5] B K1[5]

  39. Code generation – acyclic case • Static scheduling bool aux=0; if(S[1]){ if(R){aux=1;} else { if(!S[2]){ }} } else {aux=1;} if(aux){S[1..4]=1011;} S[1..4]=1011 Inactive[4] S[1] S[3] R S[3]=0 emit B K0[4] K0 emit O S[2]=1 A K1[4] K1 Inactive[5] S[2] S[4] S[4]=0 K0[5] B K1[5]

  40. Code generation – acyclic case • Static scheduling bool aux=0; if(S[1]){ if(R){aux=1;} else { if(!S[2]){ if(S[3])if(A){S[3]=0;B=1;} }} } else {aux=1;} if(aux){S[1..4]=1011;} S[1..4]=1011 Inactive[4] S[1] S[3] R S[3]=0 emit B K0[4] K0 emit O S[2]=1 A K1[4] K1 Inactive[5] S[2] S[4] S[4]=0 K0[5] B K1[5]

  41. Code generation – acyclic case • Static scheduling bool aux=0; if(S[1]){ if(R){aux=1;} else { if(!S[2]){ if(S[3])if(A){S[3]=0;B=1;} if(S[4])if(B)S[4]=0; }} } else {aux=1;} if(aux){S[1..4]=1011;} S[1..4]=1011 Inactive[4] S[1] S[3] R S[3]=0 emit B K0[4] K0 emit O S[2]=1 A K1[4] K1 Inactive[5] S[2] S[4] S[4]=0 K0[5] B K1[5]

  42. Code generation – acyclic case • Static scheduling bool aux=0; if(S[1]){ if(R){aux=1;} else { if(!S[2]){ if(S[3])if(A){S[3]=0;B=1;} if(S[4])if(B)S[4]=0; if(S[3]=0&S[4]=0){ } }} } else {aux=1;} if(aux){S[1..4]=1011;} S[1..4]=1011 Inactive[4] S[1] S[3] R S[3]=0 emit B K0[4] K0 emit O S[2]=1 A K1[4] K1 Inactive[5] S[2] S[4] S[4]=0 K0[5] B K1[5]

  43. Code generation – acyclic case • Static scheduling bool aux=0; if(S[1]){ if(R){aux=1;} else { if(!S[2]){ if(S[3])if(A){S[3]=0;B=1;} if(S[4])if(B)S[4]=0; if(S[3]=0&S[4]=0){ O=1;S[2]=1; } }} } else {aux=1;} if(aux){S[1..4]=1011;} S[1..4]=1011 Inactive[4] S[1] S[3] R S[3]=0 emit B K0[4] K0 emit O S[2]=1 A K1[4] K1 Inactive[5] S[2] S[4] S[4]=0 K0[5] B K1[5]

  44. Static analysis and optimizations • GRC specifications => usually very redundant • Optimizations • Compatible with the code generation scheme • GRC code optimizations • Software encoding optimizations • Semantic-preserving • Fast, efficient • How? Static analysis • Fast, efficient • Prepare the optimizations and the encoding • Not software-specific

  45. Static analysis and optimizations • Static analysis, example boot: trap T in sustain A || await B;await C;exit T end # nt: sustain A || await B Same status at all instants # nt: await C • Utility: • Simplify the state access/update protocol • Simplify the state encoding

  46. Static analysis and optimizations • Optimized state encoding boot: 0 trap T in sustain A || await B;await C;exit T end # 1 sustain A || await B 0 # 1 await C Unoptimized encoding: States: – boot instant – « sustain A »,« await B» active – « sustain A »,« await C» active – program terminated

  47. Static analysis and optimizations • Optimized state encoding boot: 0 trap T in sustain A || await B;await C;exit T end # nt: 1 sustain A || await B 0 # 1 nt: await C Optimized encoding: States: – boot instant – « sustain A »,« await B» active – « sustain A »,« await C» active – program terminated

  48. Static analysis and optimizations 1 boot: • Dependency removal (propagation of exclusions) 0 3 # pause; present S then emit T end; pause; emit S; 2 # 4 exit 1 enter 2 enter 3 [1] 0 emit T [2] exit 3 enter 4 S [3] 2 [4] exit 4 emit S exit 2 exit 0

  49. Static analysis and optimizations 1 boot: • Dependency removal (propagation of exclusions) 0 3 # pause; present S then emit T end; pause; emit S; 2 # 4 exit 1 enter 2 enter 3 [1] 0 emit T [2] exit 3 enter 4 S [3] 2 [4] exit 4 emit S exit 2 exit 0

  50. Static analysis and optimizations 1 boot: • Dependency removal (propagation of exclusions) 0 3 # pause; present S then emit T end; pause; emit S; 2 # 4 exit 1 enter 2 enter 3 [1] 0 emit T [2] exit 3 enter 4 S [3] 2 [4] exit 4 emit S exit 2 exit 0

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