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System On Chip

System On Chip. DAPNIA Day, November 10th Presenter : Olivier REGNAULT / SILICA FAE Xilinx. SOC Introduction. Challenge : Create High speed frequency design Use very High speed communication links Keep flexibility for modification Xilinx response :

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System On Chip

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  1. System On Chip DAPNIA Day, November 10th Presenter : Olivier REGNAULT / SILICA FAE Xilinx

  2. SOC Introduction • Challenge: • Create High speed frequency design • Use very High speed communication links • Keep flexibility for modification • Xilinx response: • FPGA provides hardware structure that enables integrated high speed design (up to 550Mhz) • FPGA offers integrated differential solution (LVDS) for DDR high speed communication + Hard IP Transceiver (Up to 3.2Gbps) • FPGA is by default the best hardware flexible solution offered through hardware reconfiguration (even partial reconfiguration) • FPGA can implement processor core as • Soft IP core (Microblaze) • Hard IP core (PowerPC)

  3. Create High speed frequency design • This is the first thing we expect from an FPGA. • What we know : • FPGA can reproduce Chip set such as DSP • FPGA enables parallel structure • FPGA integrates features to improve performance and decrease the logic needs

  4. MAC Engine FIR Filter • Several clock cycles between samples • The clock rate must be higher than the sample rate Clock Rate 550 MHz Max Sample Rate = = Number of Taps 31 = 17.7 MHz 6 12 Samplein 27 27 Samples 31 × 12 CE + × 23 D Q D Q Sample Address + 14 14 12 6 11 1 Load Coefficients 16 × 11 Coefficient Address

  5. Full Parallel FIR Filter • For the very highest sample rates, the full parallel structure performs all calculations in parallel, and registers provide the ultimate in “memory” bandwidth Registers: One per tap 6 Samplein + + + + + + + + + + + + 12 + + + + + + 12 Sample Latency Adder Tree + + + 13 + + 13 + 14 Sampleout Max Sample Rate = Clock Rate = 400 MHz (Virtex5™ FPGA) Sample rate is essentially independent of number of taps. Size is set by the number of taps

  6. Systolic FIR Filter Input time delay series is created inside the DSP48 slice for maximum performance irrespective of the number of coefficients without additional cost This filter structure, while referred to as a systolic FIR filter, is really a Direct Form with one extra stage of pipelining 12 Samplein Coefficients are from left to right, which causes the latency to be as large and grow with the increase of coefficients K0 K1 K29 K30 Sampleout 27 0 DSP48 Slice DSP48 Slice opmode = 0000101 opmode = 0010101 Max Sample Rate = Clock Rate= 550 MHz

  7. Use very high Speed communication links • Components interconnection: • Data width may be large and may require a huge number of IOBs • PCB Integrity signal  Xilinx Sparse Chevron + LVDS • Power consumption LVDS • System communication • Ethernet  Xilinx includes Tri-mode MAC Hard IP (10/1000/1000Mbps) in Virtex4 FX and Virtex5 LXT • PCI Express  Xilinx includes PCI Express Hard IP in the newest Virtex5 LXT family. • PCIe x1,x2,x4 and x8 …

  8. High-Speed Serial Applications Backplane Interface Toughest channel to drive Optics Interface SFP Modules - GE, OC-48 XFP Modules - 10GE, OC-192 Chip-to-Chip - Aurora Board-to-Board Cables, short reach optics Each Application has Unique Requirements

  9. Serial I/O + - + - Eliminates traditional noise and clock-skew issues Data Data X CDR Clk Clk 3.125 Gbps and up! Traditional I/O schemes have limited bandwidth Single Ended I/O Differential I/O(e.g., LVDS) + - Data In Data Out + - Data In Data Out Clk In Clk Out Clk Out Clk In + - + - Noise Limited above ~200 Mbps (Single Data Rate) Clock skew Limited above ~1.0 Gbps (Double Data Rate) Advantages of Serial Connectivity Transceiver Transceiver

  10. Transceiver Module TXUSRCLK TXUSRCLK2 F P G A F A B R I C Physical Coding Sublayer PhysicalMediaAttachment Mindspeed IP CRC FIFO *32/16/8 bits PC B OARD 8B / 10B Encode Serializer Transmit Buffer TX+ TXDATA TX- TX Clock Generator 50 – 156.3 MHz REFCLK Transmitter Channel Bonding and Clock Correction **20X Multiplier Loop-back Receiver CRC RX Clock Recovery *32/16/8 bits Elastic Buffer 8B / 10B Decode Deserializer Comma Det. Receive Buffer RXDATA RX+ RX- RXUSRCLK RXUSRCLK2 Transceiver Block Diagram

  11. Tx Discrete PHY Rx Tx Rx Benefits of PCIe Hard Block Soft core • Saves logic resources • 5,000 to 10,000 LUTs • Saves system cost • Saves power • Saves design time • Automated design flow • Guaranteed functionality and performance Hard core with GTP Transceivers

  12. Keep Flexibility:Processor embedded in an FPGA • Processor embedded in an FPGA consists of the following • FPGA hardware design • Software design • Software routines • Interrupt service routines (optional) • Real Time Operating System (RTOS) (optional)

  13. MicroBlaze 32-Bit RISC Core Possible in Virtex-II Pro OPB On-Chip Peripheral Bus Arbiter Custom Functions Custom Functions Memory Controller 10/100 E-Net UART MicroBlaze Processor-Based Embedded Design (Soft IP) I-Cache BRAM Local Memory Bus Flexible Soft IP BRAM Configurable Sizes D-Cache BRAM Fast Simplex Link 0,1….7 CacheLink Off-Chip Memory FLASH/SRAM SRAM

  14. RocketIO™ Dedicated Hard IP DSOCM BRAM ISOCM BRAM Flexible Soft IP PowerPC 405 Core DCR Bus Instruction Data OPB PLB Bus Bridge Arbiter Arbiter Processor Local Bus On-Chip Peripheral Bus e.g. Memory Controller Hi-Speed Peripheral GB E-Net On-Chip Peripheral UART GPIO Off-Chip Memory ZBT SSRAM DDR SDRAM SDRAM PowerPC Processor-Based Embedded Design (Hard IP) IBM CoreConnect on-chip bus standard PLB, OPB, and DCR Full system customization to meet performance, functionality, and cost goals

  15. BRAM ISOCM Controller Control Logic I-Side PLB 405 Core APU Controller D-Side PLB DSOCM Controller BRAM APU Interface • Virtex™-4 FX devices • Coprocessor interface • Connects the PowerPC™ processorto fabric • Offload computations to fabric; forexample, hardware FPU • Extends native PowerPC 405 processorinstruction set • Decodes but does not execute instructions • Tighter integration between processor and fabric

  16. Embedded Development Kit • What is the Embedded Development Kit (EDK)? • The Embedded Development Kit is the Xilinx software suite for designing complete embedded programmable systems • The kit includes all the tools, documentation, and IP that you require for designing systems with embedded IBM PowerPC™ hard processor cores, and/or Xilinx MicroBlaze™ soft processor cores • It enables the integration of both hardware and software components of an embedded system

  17. Embedded System Tools • GNU software development tools • C/C++ compiler for the MicroBlaze™ and PowerPC™ processors (gcc) • Debugger for the MicroBlaze and PowerPC processors (gdb) • Hardware and software development tools • Base System Builder Wizard • Hardware netlist generation tool: PlatGen • Software library generation tool: LibGen • Simulation model generation tool: SimGen • Create and Import Peripheral wizard • Xilinx Microprocessor Debugger (XMD) • Hardware debugging using ChipScope™ Pro Analyzer cores • Eclipse IDE-based Software Development Kit (SDK) • Application code profiling tools • Virtual platform generator: VPGen • Flash Writer utility

  18. Detailed EDK Design Flow Standard Embedded Software Flow Standard Embedded Hardware Flow Source Code (C code) MHS File system.mhs Source Code (VHDL/Verilog) MSS File system.mss Processor IP MPD Files Compile PlatGen Synthesis LibGen Object Files EDIF IP Netlists Libraries Link FPGA Implementation (ISE/Xflow) system.ucf Executable Data2MEM Create FPGA Programming (system.bit) download.bit Hardware

  19. Xilinx Solutions

  20. Embedded/ Serial Logic/Serial DSP/Serial Now Very soon 2007 Virtex-5 FPGA FamilyThe Ultimate System Integration Platform Platform Roadmap Logic Logic On-chip RAM DSP Capabilities Parallel I/Os Serial I/Os PowerPC Now Built on the Success of ASMBL * Normalized to highest quantity

  21. 5VLX30 5VLX50 5VLX85 5VLX110 5VLX220 5VLX330 Logic Cells 30,720 46,080 82,944 110,592 221,184 331,776 LUT6/FFs 19,200 51,840 69,120 138,240 207,360 28,800 Distributed RAM Kbits 320 840 1,120 2,280 3,420 480 Block RAM Kbits 1,152 3,456 4,608 6,912 10,368 1,728 CMTs 2 6 6 6 6 6 DSP48E Slices 32 48 64 128 192 48 Total I/O Banks 13 17 23 23 35 17 EasyPath No Yes Yes Yes Yes No Package Size IO FF324 19 220 220 220 FF676 27 440 400 440 440 440 FF1153 35 800 560 800 560 FF1760 42.5 1,200 1,200 800 800 X X = IO capacity Virtex-5 LX Platform

  22. Available Now! Virtex-5 LXT FPGAsIndustry’s First 65nm Serial I/O Solution • Built on Virtex-5 LX platform 65nm ExpressFabric technology • FPGA industry’s first built-in PCIe & Ethernet blocks • Compliance tested at PCISIG Plugfest and UNH IOL • Industry’s lowest power 65nm transceivers: <100mW @ 3.2Gbps • Support for all major protocols: PCIe, GbE, XAUI, OC-48, etc. • Six devices ranging from 30K to 330K logic cells 5VLX30T, 5VLX50T and 5VLX110T * Comparisons made to 90nm Virtex-4 FPGA devices

  23. Virtex-5 LXT Platform X,Y X = SelectIO, Y=RocketIO Channels

  24. Conclusion • Depending of your Digital system, you may use Xilinx FPGA as the solution for System On Chip. • Today Xilinx can provide in 1 component (Virtex4 or Virtex5): • Embedded PowerPC 405 • Embedded Ethernet MAC 10/100/1000 • Embedded MAC DSP • Embedded High Speed Transceivers • Embedded PCI Express (Virtex5 only) • Programmable Logic Cells • ….

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