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System-on-Package versus System-on-Chip?

System-on-Package versus System-on-Chip?. Docent Li-Rong Zheng Laboratory of Electronics and Computer Systems Royal Institute of Technology (KTH) SE-164 40 Kista-Stockholm, Sweden Email: lrzheng@ele.kth.se. System Implementation: SoC and SoP. SoC (System-on-Chip):

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System-on-Package versus System-on-Chip?

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  1. System-on-Package versus System-on-Chip? Docent Li-Rong Zheng Laboratory of Electronics and Computer Systems Royal Institute of Technology (KTH) SE-164 40 Kista-Stockholm, Sweden Email: lrzheng@ele.kth.se

  2. System Implementation: SoC and SoP • SoC (System-on-Chip): • A single chip integrated system or a system platform, including system hardware (digital, analog/RF) and embedded software/OS • Based on Deep Submicron (DSM) CMOS technology

  3. System Implementation: SoC and SoP • SoP (System-on-Packaging): • A convergent microsystem integrated on a microboard; also a platform based system, including hardware (digital, analog/RF, MEMS) and embedded software/OS • Based on advanced packaging and assembly technologies; • Overcome formidable integration barriers without compromising individual chip or component technologies

  4. System-on-Chip vs. System-on-Packaging • Reasons for System-on-Chip: • High performance (single chip integration/short interconnection) • Low cost (single chip integration) • Passive components (L, R, C) integration on-chip possible • Mixed signal integration (analog/RF, digital, memory) • Application example: single chip radio • Reasons for System-on-Packaging: • Single-chip integration is not necessary to be an optimal solution, • usually not possible to yield a complete system integration • - Mixed technologies in one system: Si, GeSi, GaAs, Ceramic, MEMS • - Some passive components always stay off-chip: Balun, BF, switches, antenna • - Mixed signal coupling through substrate • - Low Q for on-chip passives (2-12 c.f. 20-100 for off-chip counterparts)

  5. L=0.12µm Is the performance of SoC better than SoP ? Wires in SoC: small and resistive, signal speed 30-70ps/mm Wires in SoP: fat and lower resistive (LC transmission lines), signal speed 10-20ps/mm If we make SoP small enough, performance of SoC is not necessary better!

  6. Manufacture Cost for SoC and SoP: Millions USD for one set of photo-masks in future Deep Submicron (DSM) Chips Large SoC Chip = Low yield = high Cost Chip manufacture relays more and more on some big companies SoP substrates: Reuse of old IC fabrication lines (um to 10s micron meter technologies) Low cost substrates based on polymer materials are emerging Low cost assembly, re-work, repair

  7. Memory Integration in SoC In memory intensive SoCs, memory may occupy 50~80% chip area ! Memory integration is expensive: Embedded memories occupy larger area than the memory only die; DRAM and EEPROM: additional processing steps (trenches, folded capacitors ) are needed, which increases the cost. Embedded logic in DRAM is also expensive: DRAM process uses less metal layers Issues: Memory capacity, logic complexity, yield, package cost

  8. Memory Integration: an economic way in SoP Low performance I/Os High performance I/Os Memory SoC SRAM DRAM FRAM* EEPROM Flash Components/cell 6 1.5 1.5 2.5 1 Additional steps 0-2 4-5 4-5 4 4 * FRAM: ferroelectric RAM, a nonvolatile DRAM

  9. Mixed Signal Performance

  10. Cost for Mixed Signal Isolation 1:Increase Distance 2:Using Guarding ring 3:Special substrate: SOI, High resistivity Si Relation between isolation and distance Guard ring of heavily-doped substrate Guard ring of Lightly-doped substrate SOI technology SoP can overcome these problems by smart partitioning the chips!

  11. Cost-performance Trade-offs for RF/Mixed-Signal SoC Compromise between Quality Factor and Isolation Q Cost (distance) Isolation

  12. System-on-Chip or System-on-Package? 1. Performance:SoC is not necessary better Resistive on-chip global wire: slow, ~ 30~70ps/mm SiP: faster transmission lines, 10-20ps/mm 2. Cost:SoC is not necessary cheaper analog+logic+memory+isolation =additional cost in process and design Large chip= poor yield Cost of Test 3. Complexity and Technology Fusion:SoP is better Heterogeneous substrate: Si, GeSi, GaAs, L, R, C ... Heterogeneous technology: CMOS, bipolar, logic, memory ... 4. Other -Intellectcal Property Protection: SoP is better

  13. Logic Memory Analog/RF Performance (function) Figure-of-Merit = Cost x Time-to-Market Everything is about Cost and Performance, and also Time-to-Market, then the implementation … SoC vs. SoP: • Definition of a system • Complete Functionality • Minimum I/Os • Hardware/Software • Mixed-signal (RF, analog, digital … MEMS, optical…) • Cost & Performance • System Performance • Cost for heterogeneous integration • Cost for mixed-signal isolation • Cost for technology fusion • Intellectual property protection 1$ +1$ < 2$? 1$ +2$ > 3$? System-on-Chip system-on-package

  14. Hello, SoP ! Moore’s Law for system & packaging Moore’s Law for chip SoC &SoP SSoC SSoC ASIC, DSP, mP SoC&MCM SoC &SoP SoC &SoP Memory SoP Analog, RF MEMS OEIC year 2015? 2001 2008

  15. The Design Methodology A coherent view of system design process System Specification Initial Synthesis Performance Estimation System Partitioning Implementation: Interconnection and Technology Mapping Cost Analysis SoC ?? SoP Resource and Design Library Chip design Software Design Prototyping

  16. Conclusion SoC vs. SoP = Win and Win SoC will succeed mainly in digital systems SoP will succeed in mixed signal applications: need miniaturize in size, decrease the cost

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