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CSC 8320 Advanced Operating System Logical Clocks Suganya Gunanathan Panther# 002-30-7932

CSC 8320 Advanced Operating System Logical Clocks Suganya Gunanathan Panther# 002-30-7932 09/ 15/ 2017. Agenda. Physical Clock Logical Clock Logical Clock algorithm Lamport’s logical clock Vector clock. Physical Clocks. Need for physical clocks

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CSC 8320 Advanced Operating System Logical Clocks Suganya Gunanathan Panther# 002-30-7932

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  1. CSC 8320 Advanced Operating System Logical Clocks Suganya Gunanathan Panther# 002-30-7932 09/ 15/ 2017

  2. Agenda • Physical Clock • Logical Clock • Logical Clock algorithm Lamport’s logical clock Vector clock

  3. Physical Clocks Need for physical clocks One or more processors share a common bus, time isn't much of a concern. The entire system shares the same understanding of time: right or wrong, it is consistent. Physical clock - Multiple systems In distributed systems, this is not the case. Unfortunately, each system has its own timer that drives its clock. Each timer has different characteristics --characteristics that might change with time, temperature, etc. This implies that each systems time will drift away from the true time at a different rate.

  4. Logical Clocks • Messages sent between machines may arrive zero or more times at any point after they are sent. • If two machines do not interact, no need to synchronize them Can we order the events on different machines using local time? CausalityThe purpose of a logical clock is not necessarily to maintain the same notion of time as a reliable watch. Instead, it is to keep track of information pertaining to the order of events

  5. Lamport’s logical clock Key Ideas • Processes exchange messages • Message must be sent before received • Send/receive used to order events and to synchronize clocks • Happened before relation • Causally ordered events • Concurrent events • Implementation • Limitation of Lamport’s clock

  6. Lamport’s logical clock • Happened before relation • a -> b : Event a occurred before event b. Events in the same process p1. • b -> c : If b is the event of sending a message m1 in a process p1 and c is the event of receipt of the same message m1 by another process p2. • a -> b, b -> c, then a -> c; “->” is transitive.

  7. Lamport’s logical clock Causally Ordered Events a -> b : Event a “causally” affects event b Concurrent Events a || e: if a !-> e and e !-> a

  8. Lamport’s logical clock Algorithm Sending end time = time+1; time_stamp = time; send(message, time_stamp); Receiving end (message, time_stamp) = receive(); time = max(time_stamp, time)+1;

  9. Lamport’s logical clock • a -> b C(a) < C(b) • b -> c C (b) and C(c) must be assigned in such a way that C(b) < C(c) and the clock time, C, must always go forward (increasing), never backward (decreasing). Corrections to time can be made by adding a positive value, never by subtracting one.

  10. Lamport’s logical clock An illustration: Three processes, each with its own clock. The clocks run at different rates and Lamport's algorithm corrects the clocks.

  11. Lamport’s logical clock • Limitations • m1−>m3 • C(m1)<C(m3) • m2−>m3 • C(m2)<C(m3) • m1 or m2 caused • m3 to be sent?

  12. Lamport’s logical clock • Lamport’s logical clocks lead to a situation where all events in a distributed system are totally ordered. That is, if a -> b, then we can say C(a)<C(b). • Unfortunately, with Lamport’s clocks, nothing can be said about the actual time of a and b. If the logical clock says a -> b, that does not mean in reality that a actually happened before b in terms of real time. • The problem with Lamport clocks is that they do not capture causality. • If we know that a -> c and b -> c we cannot say which action initiated c. • This kind of information can be important when trying to replay events in a distributed system (such as when trying to recover after a crash). • The theory goes that if one node goes down, if we know the causal relationships between messages, then we can replay those messages and respect the causal relationship to get that node back up to the state it needs to be in.

  13. Vector clocks Vector clocks allow causality to be captured • Rules of Vector Clocks • Properties of a process • Implementation

  14. Vector clocks Rules and properties • A vector clock VC(i) is assigned to an event i. • If VC(i)<VC(j) for events i and j, then event i is known to causally precede j. • Each process i maintains a vector V such that – Vi [i] : number of events that have occurred at i – Vi [j] : number of events I knows have occurred at process j

  15. Vector clocks • Implementation • Before executing an event (i.e., sending a message over the network, delivering a message to an application, or some other internal event), • Pi executes VCj [i] ~ VCj [i] + 1. • When process Pi sends a message m to Pj, it sets m's (vector) timestamp ts (m) equal to VCj after having executed the previous step. • Upon the receipt of a message m, process lj adjusts its own vector by setting VCj [k] ~ max{VCj [k], ts (m )[k]} for each k, after which it executes the first step and delivers the message to the application.

  16. Vector clocks

  17. Sum Up Lamport’s timestamps • Integer clocks assigned to events • Obeys causality • Cannot distinguish concurrent events Vector timestamps • Obeys causality • By using more space, can also identify concurrent events

  18. References • Advanced Concepts in Operating Systems by Singhal and Shivaratri on pages 106-108. • Distributed Systems: Principles and Paradigms, Andrew S. Tanenbaum and Maarten Van Steen, 2016. (Second Edition) on pages 244-252 • “Time, clocks, and the ordering of events in a distributed system” by Lamport (1978) • Youtube videos https://www.youtube.com/watch?v=TH1dA7dPB2c https://www.youtube.com/watch?v=jD4ECsieFbE

  19. IEEE papers C. Lee, B. Nick, U. Brandes, and P. Cunningham, “Link prediction with social vector clocks,” in Proceedings of the 19th ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, ser. KDD ’13, Apr. 2013, pp. 784–792. M. Harrigan, “Using vector clocks to visualize communication flow.” in ASONAM, N. Memon and R. Alhajj, Eds. IEEE Computer Society, 2010, pp. 241–247. C. E. Hrischuk and C. M. Woodside, “Logical clock requirements for reverse engineering scenarios from a distributed system”, IEEE Trans. Software Eng., 28(4), Apr. 2002, 321-339. M. Raynal and M. Singhal, “Logical Time: Capturing Causality in Distributed Systems,” IEEE Computer Magazine, vol. 29, no. 2, pp. 49-56, Feb. 1996.

  20. Queries?

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