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MP3 Application on NoC-based MPSoC with Performance Metrics and Resource Management

This document outlines the application model for an MP3 processor on a Network-on-Chip (NoC)-based Multi-System-on-Chip (MPSoC). It discusses task mapping, memory management, and communication resources. The model utilizes a defined token rate for efficient processing and scheduling with potential performance metrics, including throughput and deadline miss probability. Additionally, it highlights the multi-bus communication framework, power consumption metrics, and guidelines for resource allocation between tasks. Included are special case insights into resource structuring on processor nodes.

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MP3 Application on NoC-based MPSoC with Performance Metrics and Resource Management

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  1. SIl SIr Problem 20: MP3 mapped on NoC-based MPSoC γ β RQl ROl AAl HSl FIl α α α α γ γ β β α α β γ γ β α α γ H S WB β β γ α α γ β γ β α α RQr ROr AAr HSr FIr β β γ γ α α α α β γ Application Model • SDF model (without auto-concurrency) of (modified) MP3 in a certain mode of operation • Rates are given by α = 576, β = 36 and γ = 540 tokens • All tokens have size of 1 Byte • One instance of task types H, S and WB • Two instances of task types RQ, RO, AA, HS, FI and SI

  2. Platform Battery ProcessorNode NetworkOn Chip ProcessorNode Network-On Chip Processor Node Multi Bus BufferMemory ContextMemory Processor Multi Bus BufferMemory Network-on-chip based Dual Processor Platform Platform Model • Platform is battery-powered network-on-chip based dual processor • Both processors are here assumed to be of the same type • Multi bus is communication resource offering multiple concurrent connections • Context memory temporarily stores context of tasks mapped on corresponding processor • Buffer memory temporarily stores tokens being transported over active connections • Network-on-chip includes multi bus with private buffer memory • Processor node includes processor with private context memory • Processor node includes multi bus with private buffer memory

  3. Battery ProcessorNode NetworkOn Chip ProcessorNode Platform and Mapping Platform Model • Memories can always serve requests for reservation of space (bounds to be determined) • Multi busses can always serve requests for setting up connection (bounds to be determined) • For each exchange of tokens a new connection is set up • Connection that is being set up can only become active after fixed set up delay • Processors use FCFS scheduling with fixed context switching times • Tasks require fixed amount of context memory to enable execution • Execution times of tasks are given by independent discrete uniform distributions • Memories, processors and multi busses all consume power provided by the same battery Mapping • Task is mapped on processor of a node • Channel between tasks mapped on samenode is mapped on multi bus of that node • Channel between tasks mapped ondifferent nodes is mapped on multi busof network on chip

  4. Mapping and Profiling Data Mapping Profiling Data

  5. Other Parameters Processor Node • Processor frequency 1.67·108 Hz • Context switching time for processor 1500 Cycles • Power consumption of processor 0.084 Watt • Bandwidth of each connection provided by multi bus 4·108 Bytes/Second • Latency for setting up connection by multi bus 1·10-4 Second • Power consumption of multi bus 5·10-7 Watt/Byte • Power consumption of context and buffer memory 1·10-7 Watt/Byte Network-on-Chip • Bandwidth of each connection provided by multi bus 1·108 Bytes/Second • Latency for setting up connection by multi bus 5·10-4 Second • Power consumption of multi bus 2.5·10-6 Watt/Byte • Power consumption of buffer memory 2.5·10-7 Watt/Byte WB Task • Should execute 38 times per Second • Next deadline = time of starting previous execution + 1/38 Seconds • No means to prevent deadline misses included

  6. Performance Metrics Application • Throughput of WB task (number of executions per second) • Deadline miss probability for WB task Platform • Time-average utilization of processors (load) • Time-average number of concurrent connections for each multi bus • Sum of maximum number of concurrent connections for all multi busses together • Time-average occupancy of all memories • Maximum occupancy of all memories • Nominal power consumption (time-average power consumption) • Peak power consumption (maximum power consumption) Special Case • Same problem but now with processor node modified to have a single memory for storing both the context of tasks and the tokens being transported

  7. Additional Remarks • Full details of application and platform model regarding how resources are claimed, allocated and used are discussed in accompanying pdf document • Profiling data and parameter values are somewhat tuned for the example and hence performance results do not reflect a real system • Example was developed specifically for hands-on part of tutorials at DSD’05 and FDL’05 • Contact B.D.Theelen@tue.nl

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