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Post Run13 MuTR / MuTrig Maintenance

sanam avatar
sanam
23 diapositives · 366 Views · Jul 19, 2014

This report highlights the maintenance challenges faced in the MuTr detector during Run13, specifically focusing on high noise rates at South Station-1 and the issues with HV modules and cables. We document communication failures, the need for FEE board replacements, and technical debugging processes that need to be undertaken to restore functionality. The report examines the timing misalignments between MRG and LL1, potential grounding issues, and offers references to past performance to diagnose and remedy current anomalies.

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  1. Post Run13 MuTR/MuTrig Maintenance

  2. Cathode Cable in mis-contact :South Station-1 Oct-5, Gap-2

  3. High Noise Rate in South St-1 Oct-3 Gap-2

  4. North Station-3 Octant-1 See next page for gap decomposition North Station-3 Octant-1 stands out

  5. North Station-3 Octant-1 Gap-2 <-Gap-1 is OK

  6. South HV Been bad from the past. Attempted to fix during Run12 shutdown. But couldn’t fix. Cause may be inside.

  7. MuTr HV Trip History Run13 South Lost HV module 90days * HV trip due to communication failure are excluded North N351 N331 N311

  8. Need to change FEE boards North Arm Oct-3 Anode Trippy HV 11300 S3 O2 C6 HV St-3 Oct4 N341-0 Station-1 Oct-5 Anode Trippy HV Noisy ADTX Check grounding & trippy HV 11195 S1 Q3 C3 West East 11343 S3 O7 C1 Station-2,3

  9. South Arm 11064 S2 O3 C4 11134 S3 O4 C5 Station-2,3 Noisy ADTX Check Grounding HV St3, Oct1 S311-0 (couldn’t fix) West East HV St3, Oct7 S371-6 (couldn’t fix) 11137,11138 S3 O5 C2

  10. MuTr RX Card Debugging (1) • RX card transmits electrical signal to optical. • We have only 3 spare good boards and 7 spare boards to be debugged. • To be tested at John Haggerty’s test bench. MUTR electrical optical DCM FEE RX card

  11. MuTr RX Card Debugging (2)

  12. MuTr fiber labeling • Redo MuTr fiber labeling at DCM. • The new label suppose to have Module# and dsp# as well.

  13. Debugging MRG FPGA FPGA: verilogHDL Above two octants are running with older version of MRG FPGA in Run13. Both are observable with cosmic circumstances South Octant-3 Run12 Octant-1 Cosmic SG1~50kHz South Run12 Octant-1 Physcs SG1~1kHz Plot by Dahee (Ewha University) North

  14. Backups

  15. Numbering Skeme

  16. Summary • So far high rates in both Oct-1 and Oct-3 are both disappears with down graded MRG FPGA code. • Whether we run with mixed two FPGA code? • Down grade all octants? • Confirm stability using cosmic as long as possible.

  17. When did this started? - runtype: CALIBRATION data - triggerconfig: PP510Run12_Cosmic - run time > 10 min - MUIDLL1_N1D||S_1D trigger enabled. FPGA Upgrade (Mar. 28, 2012) S_SG1 rate 40kHz Octant-3 Threshold=20mV for Cosmic Runs. FPGA Upgrade (Mar. 28, 2012) Run Rate[kHz]

  18. Run13 Threshold Response of Octant-1 Run12 Octant-1 Cosmic SG1~50kHz Run12 Octant-1 Physcs SG1~1kHz South Plot by Dahee (Ewha University) North Run12 Cosmic Rate ~40kHz is consistent with present measurement. Physics run was operated at 30mV and likely to be operated around 1kHz.

  19. Time dependent rate in Run12 Cosmic mrg_prom021 S_SG1 Rate mrg_prom036 mrg_prom036 mrg_prom036 No indication of Oct-3 High rate excursion. Hidden under Oct-1 40kHz? Need Time dependent LL1SG1 rate Oct-by-Oct -> Josh developed in the past?

  20. Long Time Monitoring Excursion

  21. Octant-1 Diagnosis • Station-1, Station-2 Mask Station-3b (done) • Chip scope measurement using LL1 fire as trigger of chip scope • Check the communication between MRG and LL1. How we know the communication error? • Check the timing alignment error. • Play with delay scan level-1 internal clock.(require LL1 FPGA modification) • Perform MRG (process) delay scan (all stations at once) more precisely (to find the timing when LL1 started to fail align),

  22. North Arm Need to change FEE boards Station-2,3 Station-1 11300 S3 O2 C6 Noisy ADTX Check grounding West East

  23. South Arm Station-2,3 Noisy ADTX Check Grounding West East