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Li Jiang 1 , Qiang Xu 1 , Krishnendu Chakrabarty 2 , and T. M. Mak 3

Layout-Driven Test-Architecture Design and Optimization for 3D SoCs under Pre-Bond Test-Pin-Count Constraint. Li Jiang 1 , Qiang Xu 1 , Krishnendu Chakrabarty 2 , and T. M. Mak 3 1 Deptartment of CS&E, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong

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Li Jiang 1 , Qiang Xu 1 , Krishnendu Chakrabarty 2 , and T. M. Mak 3

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  1. Layout-Driven Test-Architecture Design and Optimizationfor 3D SoCs under Pre-Bond Test-Pin-Count Constraint Li Jiang1, Qiang Xu1, Krishnendu Chakrabarty2, and T. M. Mak3 1Deptartment of CS&E, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong 2Deptartment of ECE, Duke University, Durham, NC 3Intel Corporation, Santa Clara, CA

  2. Outline • Background • Motivation • Approach • Experiments • Conclusion

  3. Background • TSV Technique • Benefit of 3D IC • Interconnect • Performance • Power • Memory Bandwidth • Heterogeneous Integration 1. Gabriel H. Loh. 3D-Stacked Memory Architectures for Multi-Core Processors. ISCA. 2008

  4. Background • Pre-bond Test • W2W • Simplicity of the Manufacturing Process • Low Yield • D2D & D2W • Pre-bond Test • High Yield

  5. Background • Test Architecture Design • IEEE P1500 Standard • TAM Manner • TSV • Pad • Additional Pad • Primary Pad • Routing Model • TAM Segment

  6. Background • Test-Pin-Count Constraint • Fine-grained Touchdown Probe Needles Unavailable • Impossible to fabricate a large number of test pads for pre-bond testing • Area of Pad • Probe Force to the Thinned Wafer

  7. Outline • Introduction • Motivation • Approach • Experiments • Conclusion

  8. Motivation • Separate Test Architectures for Pre-bond Tests and Post-bond Test • Share the Routing Resources

  9. Problem Definition • Given • Set of Cores • Test Parameters (Scan chain, Pattern, Input/Output) of each core • Physical Position of Each Core • Maximum available TAM width • pre-bond test-pin-count constraintWpre; • Determine • Number of TAM • Core Assignment • Width of each TAM • Objectivity • minimize the total test cost

  10. Total Test Cost • Test Cost Model • Ctotal = CTest-Time * α+ CWire-Length *(1- α) • CTest-Time = CTest-Chip + Σ CTest-Layer • CWire-Length depends on routing model • Routing Model • Manhattan Distance • TAM Segment • TSP3 3.S. Goel and E. Marinissen. Layout-driven SOC test architecture design for test time and wire length minimization. In Proceedings IEEE/ACM Design, Automation and Test in Europe Conference and Exhibition, pages 738–743, 2003.

  11. Outline • Introduction • Motivation • Approach • TAM Wire Reuse with Fixed Test Architectures • TAM Wire Reuse with Flexible Pre-bond Test Architecture • Experiments • Conclusion

  12. TAM Wire Reuse with Fixed TestArchitectures • Test Architecture Optimization for Both Post-bond Test and Pre-bond Test • Fix the TAM (width, core assignment) • Post-bond TAM Routing • Identification of Reusable TAM Segments • Pre-bond TAM Routing

  13. TAM Wire Reuse with Fixed TestArchitectures • Post-bond TAM Routing • Construct the Complete Graph • Sort Edges • Greedy Choose • Update the Candidates • Not TSP

  14. TAM Wire Reuse with Fixed TestArchitectures • Identification of Reusable TAM Segments • Manhattan Distance and Bounding Rectangles • Overlapping Bounding Rectangles • Impact of Relative Slope

  15. TAM Wire Reuse with Fixed TestArchitectures • Pre-bond TAM Routing • Get Possible Reusable Post-bond TAM Segments • Construct Completed Graph Gi for Every Pre-bond TAM in the layer, and put all Gi together into SG. • Build List for Each Pre-bond TAM Segment, Store All Possible Reusable Candidates into the List Combined with the Routing Cost after Reuse. • Sort the list According to the Routing Cost • In Every Iteration, • Choose the Segment with Least Routing Cost • Move it into EG • Delete this Reused Segment from all other edges in SG • Update the Candidate Segment • Obtain the Routing Result and its Cost

  16. TAM Wire Reuse with Fixed TestArchitectures • Example

  17. TAM Wire Reuse with Flexible Pre-bond Test Architecture • Change test architecture for pre-bond tests, further reduce their routing cost • Sacrifice only limited testing time

  18. TAM Wire Reuse with Flexible Pre-bond Test Architecture • Outer SA-based Core Assignment • Rules • Redundancy • Two ascending order • If i<j, keep the smallest core index assigned to TAM i smaller than that assigned to TAM j • Prove of completeness

  19. TAM Wire Reuse with Flexible Pre-bond Test Architecture • Inner TAM Width Allocation Procedure • Short running time • Greedy Heuristic • Close-to-optimal Solution4 4. S. K. Goel and E. J. Marinissen. Effective and Efficient Test Architecture Design for SOCs. In Proceedings IEEE International Test Conference (ITC), pages 529–538, Baltimore, MD, Oct. 2002.

  20. Outline • Introduction • Motivation • Approach • Experiments • Conclusion

  21. Experiments Results

  22. Experiments Results

  23. Experiments Results

  24. Outline • Introduction • Motivation • Approach • Experiments • Conclusion

  25. Conclusion • Only fabricate a limited number of test pads for pre-bond testing • Dedicated pre-bond and post-bond test architectures to satisfy the given test pad constraint • Novel layout-driven optimization techniques to share the TAM routing resources between pre-bond tests and post-bond test

  26. Thank You Q & A

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