Appendix

1. Appendix

2. nextpc p ② ① The value of program count is maintained Program counter’s value is selected when diverging Control of instruction ④ Execution part of operation according to instruction Instruction is load Data RAM or not ⑥ ③ ⑦ ⑧ ⑤ Select register operation or operation Instruction The address of the written register is selected by the instruction(※Instruction Set) The value of the register is rewritten, and output.

3. 32bitregister ① Program Counter • 32 bit register • Synchronize with Clock • Reset by signal Reset ・example process(Clock, Reset) begin if(Reset='1') then pc <= (others=>'0'); elsif(Clock'event and Clock='1') then pc <= nextpc; end if; end process; nextpc 32 pc 32 Reset Clock

4. ② PC MUX • Select nextpc ・example nextpc <=branchadd when op=OP_BEQ and zero='1' else jumpadd when op=OP_J else pnext; pnext 32 nextpc jumpadd 32 32 MUX branchadd 32 op 6 zero ※”next” is reserved name. “next”→”pnext”

5. ③ WAMUX • Select wa. This is Write Address in RF. ・example wa <=rd when op=OP_ALU else rt; rt 5 rd 5 wa 5 MUX op 6

6. 32 × 32 Register File ⑤ Register file writeRF ・example Process (Clock, Reset) begin if (Reset='1') then for i in 0 to 31 loop REG (i) <= X"00000000"; end loop; elsif (Clock'event and Clock='1') then if (writeRF='1') then REG (conv_integer (wa)) <= din; end if; end if; end process; do1 <= REG(conv_integer(ra1)); do2 <= REG(conv_integer(ra2)); 32 do1 5 ra1 5 ra2 5 wa 32 din Reset 32 do2 Clock

7. ⑥ sr2 MUX • Select sr2 se 32 ・example sr2 <= se when op=OP_SW or op=OP_LW else do2; do2 32 sr2 32 MUX op 6

8. ⑦ ALU ・example result <= sr1 - sr2 when (op=OP_ALU and (func=FN_SUB or func=FN_SLT)) or op=OP_BEQ else sr1 and sr2 when op=OP_ALU and func=FN_AND else sr1 or sr2 when op=OP_ALU and func=FN_OR else sr1 + sr2; zero <= '1' when sr1=sr2 else '0'; zero sr1 32 ALU op 6 result 32 func 6 sr2 32

9. ⑧ din MUX • Select din ・example din <= Rddata when op=OP_LW else X"00000001" when op=OP_ALU and func=FN_SLT and result(31)='1' else X"00000000" when op=OP_ALU and func=FN_SLT else result; result 32 Rddata 32 din 32 MUX op 6 func 6

10. Others(1) ・example pnext <= pc + X"00000004"; Iadd <= pc(7 downto 2); op <= Inst(31 downto 26); func <= Inst(5 downto 0); rs <= Inst(25 downto 21); rt <= Inst(20 downto 16); rd <= Inst(15 downto 11); offset <= Inst(15 downto 0); address <= Inst(25 downto 0); se <= X"ffff" & offset when offset(15)='1' else X"0000" & offset; se4 <= se(29 downto 0) & "00"; branchadd <= se4 + pnext; jumpadd <= pnext(31 downto 28) & address & "00"; ra1 <= rs; ra2 <= rt; writeRF <= '1' when op=OP_ALU and (func=FN_ADD or func=FN_SUB or func=FN_SLT or func=FN_AND or func=FN_OR) else '1' when op=OP_LW else '0'; sr1 <= do1; Wtdata <= do2; WE <= '1' when op=OP_SW else '0'; Dadd <= result(7 downto 2);

11. Others(2) signal pc, nextpc, pnext, branchadd, jumpadd, se, se4, din, do1, do2, sr1, sr2, result: std_logic_vector(31 downto 0); signal address: std_logic_vector(25 downto 0); signal offset: std_logic_vector(15 downto 0); signal op, func: std_logic_vector(5 downto 0); signal rs, rt, rd, ra1, ra2, wa: std_logic_vector(4 downto 0); signal zero, writeRF: std_logic; subtype reg32_t is std_logic_vector(31 downto 0); type reg_file is array (0 to 31) of reg32_t; signal REG: reg_file;