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Biography for William Swan

Biography for William Swan.

660 views • 55 slides

Lecture 3: Memory Buffers and Scheduling

Lecture 3: Memory Buffers and Scheduling. Topics: buffers (FB-DIMM, RDIMM, LRDIMM, BoB, BOOM), memory blades, scheduling policies. HMC Details. 32 banks per die x 8 dies = 256 banks per package 2 banks x 8 dies form 1 vertical slice (shared data bus)

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213 views • 21 slides

GENERAL

GENERAL. Inspired by LeCroy ULM Originally designed for MSU specs 72 ECL Ports XCS40XL FPGA TMS320C6711 floating point DSP (900 Mflops/s) 2 banks of fast asynchronous SRAM 2-Mbytes/ea VMEbus interface Internal clock rate 80 MHz 25 Mbyte/s actual transfer rate. Interface. FPGA.

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250 views • 8 slides

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Biography for William Swan

Lecture 3: Memory Buffers and Scheduling

GENERAL