L1a - PowerPoint PPT Presentation

KOTO CDT Module Status Report

KOTO CDT Module Status Report. Mircea Bogdan The University of Chicago 10/13/2016. New CDT - Block Diagram – 8/27/2016. Minor changes to the Old MT Board: Same FPGA Same TLK chips The Changes are: 4 TLK Chips 16 x RJ45 to ADCs 2 x RJ45 to Master Clock Jitter Cleaner.

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124 views • 10 slides

CSC Synchronization Procedure and Plans

CSC Synchronization Procedure and Plans. Updated July 29, 2005 Jay Hauser / David Matlock / Yangheng Zheng University of California, Los Angeles Martin Von der Mey Fermilab. What is done now What should be done. Overview: Step I, without needing L1A.

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195 views • 7 slides

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