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Mux4to1 port map - PowerPoint PPT Presentation

Figure 6.1. A 2-to-1 multiplexer.

s. f. s. w. w. 0. 0. 0. 0. f. w. 1. w. 1. 1. 1. (b) Truth table. (a) Graphical symbol. w. w. 0. 0. s. s. f. w. w. f. 1. 1. (d) Circuit with transmission gates. (c) Sum-of-products circuit. Figure 6.1. A 2-to-1 multiplexer. s. 0. s. s. s. f. 1. 1. 0. w.

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CS/EE 3700 : Fundamentals of Digital System Design

CS/EE 3700 : Fundamentals of Digital System Design. Chris J. Myers Lecture 6: Combinational Blocks Chapter 6. s. f. s. w. w. 0. 0. 0. 0. f. w. 1. w. 1. 1. 1. (b) Truth table. (a) Graphical symbol. w. w. 0. 0. s. s. f. w. w. f. 1. 1.

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Flip-flops

Flip-flops. Combinational logic circuit. Basic Latch. Both circuit are the same The only feedback path is the red line. Basic Latch. Consider Set = 0, Reset =0. Basic Latch. Consider S = 1, R =0 As S=1, NOR1 output must be 0 As NOR1 ouput = 0 and R =0, NOR2 output must be 1. Basic Latch.

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Mux4to1 port map - PowerPoint PPT Presentation

Figure 6.1. A 2-to-1 multiplexer.

CS/EE 3700 : Fundamentals of Digital System Design

Flip-flops