'Sleep transistors' diaporamas de présentation

Power, Temperature, Reliability and Performance - Aware Optimizations in On-Chip SRAMs

Power, Temperature, Reliability and Performance - Aware Optimizations in On-Chip SRAMs. Houman Homayoun PhD Candidate Dept. of Computer Science, UC Irvine. Outline. Past Research Low Power Design

1.02k views • 85 slides

LOW-LEAKAGE REPEATERS FOR NETWORK-ON-CHIP INTERCONNECTS

509 views • 30 slides

Timepix2 power pulsing and future developments

Timepix2 power pulsing and future developments. X . Llopart 17 th March 2011. Timepix2 Scope. Several groups in the Medipix3 collaboration have shown interested in a new version of the Timepix ? Timepix2 Large range of applications (HEP and non-HEP):

326 views • 14 slides

Multiple Sleep Mode Leakage Control for Cache Peripheral Circuits in Embedded Processors

Multiple Sleep Mode Leakage Control for Cache Peripheral Circuits in Embedded Processors. Houman Homayoun, Avesta Makhzan, Alex Veidenbaum Dept. of Computer Science, UC Irvine hhomayou@ics.uci.edu. On-chip Caches and Power . On-chip caches in high-performance processors are large

190 views • 8 slides