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cms tracker fed cms tracker two weekly meeting design update rob halsall et al 18 july 2001 ral n.
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CMS Tracker FED CMS Tracker Two Weekly Meeting Design Update Rob Halsall et al 18 July 2001 RAL PowerPoint Presentation
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CMS Tracker FED CMS Tracker Two Weekly Meeting Design Update Rob Halsall et al 18 July 2001 RAL

CMS Tracker FED CMS Tracker Two Weekly Meeting Design Update Rob Halsall et al 18 July 2001 RAL

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CMS Tracker FED CMS Tracker Two Weekly Meeting Design Update Rob Halsall et al 18 July 2001 RAL

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  1. CMS Tracker FEDCMS Tracker Two Weekly MeetingDesign Update Rob Halsall et al18 July 2001RAL

  2. CMS Tracker FED96 ADC Module 1.5V Temp Sense 5V I2C FLASH ?V 3V 2.5V 5V 3V 2.5V 1.5V 1 1 1 Opto Rx Prog Delay 1 1 Dual ADC I2C FE 1 FPGA config FPGA Synch & Processing -5V VME VME Interface SBC ASIC BScan PD Array 6 12 way FR 4 Prog Delay Dual ADC 12 FPGA FPGA FPGA 2 Temp Sense I2C SSRAM ?V X DAQ Readout & Synch Control TTS FPGA Temp Sense I2C 85 1 1 clk40 43 Prog Delay Opto Rx 8 8 Dual ADC 9 FPGA FE 8 TTCrx Synch & Processing ASIC ASIC PD Array 6 12 way FR 48 4 Prog Delay 96 Dual ADC FPGA FPGA Temp Sense I2C BSCAN TTC FPGA

  3. CMS Tracker FEDSystem Timing 256+12 #2234 Header Data ADC Output Frame Sync Out Auto Sync(s) Status Message Frame Sync In Handshake Message Readout Sync Out #2233 Processed Message #2220 #2221 Readout Message Readout Message Readout Sync In #2219 #2220 #2221 Data Burst Data Burst Data Burst Data

  4. CMS Tracker FED Front End FPGA Clock40 Reset ADC_Data_stream 0 Mode Load/Run Frame_Sync_out Frame_Sync Frame_Sync_In Readout_Sync_out delay_ser_out Readout_Sync Readout_Sync_In delay_ser_in Front End FPGA Monitor_Sync_out Monitor_Sync & Serial_Load Monitor_Sync_In Data_stream ADC_Data_stream 11 Full Flags

  5. CMS Tracker FED Back End FPGA Clock40 Frame_Sync_out0 Reset Frame_Sync_In0 VME Internal Readout_Sync_out0 Readout_Sync_In0 FE0 SLINK64 Monitor_Sync_out0 Monitor_Sync_In0 TTS Data_stream0 Frame_Sync_out7 Frame_Sync_In7 TTC Readout_Sync_out7 Readout_Sync_In7 FE1 ADDRESS Monitor_Sync_out7 Monitor_Sync_In7 DATA IN QDR SSRAM DATA OUT Data_stream7

  6. CMS Tracker FED Back End FPGA x2 BSCAN Clock40 x4 DCM x1 diagnostics Circular Buffers 64 64 ‘VME’ SLINK monitoring 80 MHz Reset Halt APV hdrs x8 FIFO Frame_Syncs x8 DECODE CONTROL & MONITOR Lengths Readout_Syncs x8 16 FIFO Data Out Monitor_Syncs 320 MHz Bx,Ex 40 Mhz QDR SSRAM x4 burst FIFO Lengths Em Hdr R/W Address Generator 9 TTC Rx 20 Address FIFO TTS 80 MHz Header 100 Khz 8 Data_stream0 64 16 Data In 80 Mhz 8 320 MHz Data_stream7 80 MHz

  7. CMS Tracker FED Back End FPGA #FFFFF Event N+1 Event N+1 Event N+1 Write Ptr 7 FE 7 Write Ptr 7 Write Ptr 7 Write Ptr 2 Event N Write Ptr 2 Write Ptr 2 Write Ptr 1 FE 1 Write Ptr 0 Write Ptr 1 Write Ptr 1 FE 0 Header Ptr Write Ptr 0 Write Ptr 0 Header Ptr Header Ptr Read Ptr Event N-1 Event N-1 Event N-1 Read Ptr Read Ptr #00000 T0 T1 T2

  8. CMS Tracker FEDSynch & Processing FPGA Synch & Processing FPGA 1x per adc channel phase compensation required to bring data into step Clock 40 MHz 2x DLL 4x Synch in Synch out 2 x 256 cycles 256 cycles nx256x16 Synch emulator in trig2 trig3 trig4 trig1 Synch error Re-order cm sub Phase Registers 10 11 11 s-data 16 10 10 8 Hit finding 16 sync ADC 1 Ped sub d d DPM Global reset 8 s-addr hit Sub resets 8 8 Sequencer-mux a a Control No hits Full flags 8 header status averages control mux 4x data 8 ADC 12 Packetiser 256 cycles 256 cycles nx256x16 trig1 trig2 trig3 Re-order cm sub Phase Registers 10 11 11 s-data 16 10 10 8 16 sync Hit finding Ped sub d d DPM 8 s-addr Serial I/O hit 8 8 Sequencer-mux a a Serial Int No hits 8 header status averages Opto Rx Local IO Opto Rx Delay Line B’Scan Config

  9. adc adc adc adc adc adc DSP adc adc ASIC adc adc adc adc DSP adc adc ASIC adc adc adc adc DSP adc adc ASIC adc adc adc adc DSP adc adc ASIC adc adc adc adc DSP adc adc ASIC adc adc adc adc DSP adc adc ASIC adc adc adc DSP adc ASIC adc CMS Tracker FED System OverviewBoard Layout 96 ADC Channels 360 MByte/s FE 1 adc FE FPGA adc ASIC VME FPGA VME ’ 360 MByte/s FE 2 FE FPGA 360 MByte/s FE FPGA FE 3 360 MByte/s Sync error FE 4 FE FPGA DAQ PMC Full flags prog’ prog’ delay delay Emulator RO FPGA Reset(s) 360 MByte/s FE 5 NN Synch FE FPGA B Scan 360 MByte/s FE 6 FE FPGA TTCrx ASIC 100 KHz TTC 360 MByte/s FE FPGA FE 7 150 MByte/s/% DAQ 360 MByte/s adc FE 8 FE FPGA adc adc