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ECE4430 Project Presentation

ECE4430 Project Presentation. OPERATIONAL AMPLIFIER GROUP3 – DEBASHIS BANERJEE JASON PINTO ASHITA MATHEW. DESIGN SPECIFICATIONS. Technology Node – TSMC 0.18µm Required Design Specifications. BMR & BIASING CIRCUIT.

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ECE4430 Project Presentation

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  1. ECE4430 Project Presentation OPERATIONAL AMPLIFIER GROUP3 – DEBASHIS BANERJEE JASON PINTO ASHITA MATHEW

  2. DESIGN SPECIFICATIONS Technology Node – TSMC 0.18µm Required Design Specifications ECE 4430 Project2 Presentation

  3. BMR & BIASING CIRCUIT ECE 4430 Project2 Presentation

  4. OPERATIONAL AMPLIFIER -TOPOLOGY USED ECE 4430 Project2 Presentation

  5. Transconductance stabilization circuit Literature reference : M.M. Ahmadi, R. Lotfi, M. Sharif-Bakhtiar, “A New Architecture for Rail-to-Rail Input Constant-gm, CMOS OperationaI Transconductance Amplifiers ” , ISLPED ‘03 ECE 4430 Project2 Presentation

  6. INITIAL DESIGN STEPS • Redesigned BMR with 5uA reference current • Designed short channel biasing circuit • Total current budget = 75uA for a max power consumption of 150uW • The transconductances of the PMOS NMOS pair of amplifying devices were made equal by sizing the PMOS to NMOS in the ratio kpn:kpp (5:1) • Current combining stage is made low voltage headroom cascode with floating current sources for proper biasing. • The transconductance stage of diffamp was biased with 5uA each and the summing stage was designed for a current of 30uA • For a rail to rail output swing, we designed a class AB push pull amplifier • Using CC= 0.22CL caused the bandwidth to be about 100Hz only. • Compensation capacitor was fine tuned iteratively to achieve a desired phase margin and maximum bandwidth possible. ECE 4430 Project2 Presentation

  7. MAGNITUDE- PHASE PLOT ECE 4430 Project2 Presentation

  8. ICMR : - 0.4 V to 2.23V PHASE MARGIN OVER vcm 90.32dB, 2.23V 90.32dB, -0.41V 56 degrees 50.09 degrees ECE 4430 Project2 Presentation

  9. OUTPUT VOLTAGE SWING : 0 - 2V -0.25 V , 93dB 2.25V, 88dB 90.32dB, -0.41V 90.32dB, 2.23V ECE 4430 Project2 Presentation

  10. SLEW RATE Rise time = 175 ns Fall time = 171ns No ringing observed in output waveform. Settling time =0 Positive slew rate = 9.224 V/us Negative slew rate = -9.275 V/us ECE 4430 Project2 Presentation

  11. MINIMUM AND MAXIMUM SUPPLY VOLTAGE ECE 4430 Project2 Presentation

  12. CMRR ACHIEVED = 140dB ECE 4430 Project2 Presentation

  13. PSRR FOR VDD MEASUREMENT OF PSRR 108.8 dB PSRR FOR GND 108.8 dB ECE 4430 Project2 Presentation

  14. INPUT REFERRED NOISE 35.57nV/sqrt(Hz) ECE 4430 Project2 Presentation

  15. GAIN BANDWIDTHS Unloaded BW = 434 Hz Loaded GBW = 17.36 MHz Unloaded GBW = 18.04 MHz ECE 4430 Project2 Presentation

  16. INPUT OFFSET VOLTAGE = -2.01uV MEASUREMENT OF INPUT OFFSET VOLTAGE NOMINAL OUTPUT VOLTAGE = 0.8 V ECE 4430 Project2 Presentation

  17. POWER CONSUMPTION CURVES without load with load ECE 4430 Project2 Presentation

  18. Op-Amp Final Specs and Simulation Results: ECE 4430 Project2 Presentation

  19. DEVIATION FROM SPECS ECE 4430 Project2 Presentation

  20. CONCLUSION • We observed that increasing the compensation capacitance improves the phase margin at the cost of bandwidth. • For our case, the degradation in phase margin did not trade off for an appreciable increase in bandwidth. • Better common mode rejection was achieved by cascoding the tail current sources. • A gain of 95dB is not significantly deviated from 100dB because the OPAMP operates mainly as a feedback amplifier. • Since phase margin is high enough, no ringing is observed for a step response ECE 4430 Project2 Presentation

  21. Thank you… Questions?? ECE 4430 Project2 Presentation

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