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Input/Output

Input/Output

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Input/Output

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  1. Input/Output CIS 345/545

  2. Input/Output • A computer system has three major components: • CPU • Memories (primary and secondary) • I/O (Input/Output) equipment • printers • scanners • modems • etc.

  3. Buses • Physically, most PCs have a structure similar to that shown on the next slide. • The PC contains a metal box with a large printed circuit board (the motherboard) at the bottom. The motherboard contains: • CPU chip • Slots for DIMM modules • Various support chips • A bus etched along its length (maybe two) • Sockets into which the edge connectors of I/O boards can be inserted.

  4. Physical Structure of a PC

  5. Buses • Each I/O device consists of two parts: • the controller, which contains most of the electronics • the I/O device itself • The controller is usually on a board plugged into a free slot, except for those controllers which are not optional which are sometimes located on the motherboard. • The monitor is not optional, but the video controller is sometimes located on a plug-in board to allow the user to choose the type of display.

  6. Logical Structure of a PC

  7. Computer Buses • A bus is a common electrical pathway between multiple devices. • Can be internal to the CPU to transport data to and from the ALU. • Can be external to the CPU, to connect it to memory or to I/O devices. • Early PCs had a single external bus or system bus. • Modern PCs have a special-purpose bus between the CPU and memory and (at least) one other bus for the I/O devices.

  8. Computer Buses

  9. Computer Buses • In order to make it possible for boards designed by third parties to attach to the system bus, there must be well-defined rules about how the bus works, and which all attached devices must obey. • These rules are called the bus protocol. • In addition, there must be mechanical and electrical specifications.

  10. Computer Buses • A number of buses have been widely used in the computer world. • Multibus (8086) • IBM PC (PC/XT) • ISA bus (PC/AT) • EISA bus (80386) • Microchannel (PS/2) • PCI bus (Many PCs) • Nubus(Macintosh) • Universal Serial Bus (modern PCs) • FireWire (consumer electronics)

  11. Computer Buses • Some devices that attach to a bus are active and can initiate bus transfers. They are called masters. • Some devices are passive and wait for requests. They are called slaves. • Some devices may act as slaves at some times and masters at others. • Memory can never be a master device.

  12. Buses • The job of a controller is to control its I/O device and handle bus access for it. • A controller that reads or writes data to or from memory without CPU intervention is said to be performing Direct Memory Access (DMA). • When the transfer is finished, the controller issues an interrupt, forcing the CPU to switch from the running program to an interrupt handler. After this, the OS can resume the suspended job.

  13. Direct Memory Access (DMA) • Figure 5-4. Operation of a DMA transfer.

  14. Memory-Mapped I/O (1) • Figure 5-2. (a) Separate I/O and memory space. (b) Memory-mapped I/O. (c) Hybrid.

  15. Buses • The bus is used by both I/O controllers and the CPU. When both want to use the bus, a bus arbiter decides who will go next. In general, I/O devices are given precedence since disks and other moving devices cannot be stopped without losing data. • When no I/O is in progress, the CPU has all the bus cycles for itself to reference memory. When some I/O device is also running, it will request and be granted the bus. This is called cycle stealing and it slows down the computer.

  16. Interrupts Revisited • Figure 5-5. How an interrupt happens. The connections between the devices and the interrupt controller actually use interrupt lines on the bus rather than dedicated wires.

  17. Precise and Imprecise Interrupts (1) • Properties of a precise interrupt • PC (Program Counter) is saved in a known place. • All instructions before the one pointed to by the PC have fully executed. • No instruction beyond the one pointed to by the PC has been executed. • Execution state of the instruction pointed to by the PC is known.

  18. Precise and Imprecise Interrupts (2) • Figure 5-6. (a) A precise interrupt. (b) An imprecise interrupt.

  19. Buses - Standardization • As CPUs, memories and I/O devices became faster, the bus could no longer handle the load. • Replacing the bus every time it became overloaded with a higher capacity one would cause the old peripherals to become useless. • Therefore many manufacturers stayed with the old ISA (Industry Standard Architecture) bus. Eventually companies started developing computers with multiple buses including the ISA, the backward-compatible EISA (Extended ISA), and now PCI (Peripheral Component Interface).

  20. PC with PCI and ISA Buses

  21. Interrupt Controllers • When the CPU commands an I/O device to do something, it usually expects an interrupt when the work is done. The interrupt signaling requires the bus. • Since multiple devices may want to cause an interrupt simultaneously, the same kind of arbitration problems as with ordinary bus cycles are present. • The usual solution is to assign priorities and use a centralized arbiter.

  22. Interrupt Controllers • Standard interrupt controller chips exist and are widely used. • The IBM PC and all its successors use the Intel 8259A chip. • Up to eight I/O controllers can be directly connected to the eight IR inputs to the 8259A. When one of these devices wants to cause an interrupt, it asserts its input line. • When one or more interrupts are asserted, the 8259A asserts INT which drives the interrupt pin on the CPU.

  23. Interrupt Controllers • When the CPU is able to handle the interrupt, it sends back a pulse on INTA. • At that point, the 8259A specifies which input caused the interrupt by outputting the input’s number on the data bus. • The CPU uses that number to index into a table of pointers called interrupt vectors, to find the address of the procedure to run to service the interrupt. • Several 8259As can be cascaded to handle more than eight I/O devices.

  24. Interrupt Controllers

  25. Example Buses - The ISA Bus • The IBM PC bus was the de facto standard on 8088-based systems because nearly all PC clone vendors copied it to allow existing third-party I/O boards to be used with their systems. • It had 62 signal lines, including 20 for a memory address, 8 for data, and one each for asserting memory read, write, I/O read and write. • The bus was etched onto the PCs motherboard with about half a dozen connectors for cards.

  26. The ISA Bus

  27. The ISA Bus • With the introduction of the 80286, IBM extended the PC bus. New cards had an extra edge connector at the bottom. • With the introduction of the PS/2, IBM introduced a new bus, the Microchannel bus which was protected by patents. • The rest of the industry reacted by adopting the ISA (Industry Standard Architecture) bus as a standard. • This is basically a PC/AT bus running at 8.33 MHz.

  28. Example Buses - The PCI Bus • With the introduction of GUIs, the ISA bus was no longer sufficiently powerful. • In 1990, Intel designed a new bus with a much higher bandwidth than ISA or even EISA. It was called the PCI bus (Peripheral Component Interconnect bus). • To encourage its use, Intel patented the PCI bus and then put all the patents into the public domain. Intel also formed an industry consortium to manage the future of the PCI bus.

  29. The PCI Bus • As a result, the PCI bus became extremely popular. • The original PCI bus had a bandwidth of 133 MB/sec (32 bits per cycle and 33 MHz frequency - 30 nsec cycle time). • PCI 2.2 runs at up to 528 MB/sec. • In order to allow computers incorporating PCI buses to contain old peripherals, Intel designed computers with three or more buses. • The buses are connected by bridge chips (manufactured by Intel).

  30. The PCI Bus

  31. Pentium 4 Buses

  32. The PCI Bus • There are a variety of PCI card types: • 5 or 3.3 volts • 32-bit or 64-bit • 33 MHz or 66 MHz • The PCI bus is synchronous. All transactions are between a master and a slave. • The address and data pins are multiplexed, thus only 64 pins are needed for address and data. • The PCI bus uses a centralized bus arbiter. The arbiter is usually built into one of the bridge chips.

  33. The PCI Bus

  34. The PCI Bus • The algorithm used by the arbiter is not defined by the PCI specification. • The PCI bus has a number of mandatory signals and a number of optional signals. The remainder of the 120 (32-bit version) or 184 pins (64-bit version) are used for power, ground, and related miscellaneous functions.

  35. PCI Express • The new PCI Express architecture does away with the bus • Replaced with a switch which has 2 unidirectional serial links to all I/O devices • Devices send data packets to other devices • Header of the packet contains control info • An I/O device may actually be another switch • The serial links are much smaller than PCI bus • Devices are hot pluggable • Error detection in the packets

  36. PCI Express A typical PCI Express system.

  37. The Universal Serial Bus • The PCI bus is fine for attaching high-speed peripherals to a computer, but is far too expensive to have a PCI interface for each low-speed I/O device. • Traditionally, new peripheral devices were inserted in free ISA and PCI slots. This can cause problems since the user is often responsible for setting switches and jumpers on the card and checking for conflicts with other cards. The user must open the case and insert the card then reboot the computer.

  38. The Universal Serial Bus • Representatives from seven companies designed a better way to attach low-speed I/O devices to a computer. The resulting standard is called USB (Universal Serial Bus). • The goals of the project were: • No jumpers or switches to set • User doesn’t have to open the case • Only one kind of cable • I/O devices get power from the cable • Up to 127 devices attachable to a single computer • Real-time device support

  39. The Universal Serial Bus • Devices installable while the computer runs • No reboot after installing a new device • Inexpensive to manufacture • USB meets these goals. • The total USB 1.1 bandwidth is 1.5 MB/sec. • A USB system consists of a root hub that plugs into the main bus. This hub has sockets for cables that attach to I/O devices. I/O devices also have sockets for additional devices. • The topology of a USB system is a tree.

  40. The Universal Serial Bus • When a new I/O device is plugged in, the root hub detects the event and interrupts the OS. • The OS then queries the device to find out what it is and how much bandwidth it needs. • If the OS decides there is enough bandwidth available, it assigns the device a unique address (1-127) and downloads this address and other info to configuration registers inside the device.

  41. The Universal Serial Bus • A USB system may be viewed as a set of bit pipes from the root hub to the I/O devices • Within the pipes, data (frames) flow from the root hub to the I/O device or vice versa • The root hub continuously broadcasts frames to keep the devices synchronized • Frames consist of one or more packets

  42. The Universal Serial Bus The USB root hub sends out frames every 1.00 ms.

  43. USB 2.0 • USB 2.0 is a newer faster version • Bandwidth is 60 MB • Backwards compatible with USB 1.1 devices • Comparable speed to FireWire - a consumer electronics interface for digital camcorders, DVD players, etc.

  44. Magnetic Disks • A magnetic disk consists of one or more aluminum platters with a magnetizable coating. They are typically 3 to 12 cm in diameter. • A disk head floats over the surface of the disk. The disk head can magnetize the surface or read the bits previously stored. • The circular sequence of bits written as the disk makes a complete rotation is called a track. Each track is divided into fixed-length sectors.

  45. Magnetic Disks • Sectors typically consist of a preamble (for head synchronization), followed by 512 data bytes. Following the data is an Error-Correcting Code, either a Hamming code, or more commonly, a code that can correct multiple errors called a Reed-Solomon code. Between consecutive sectors is a small intersector gap. • Disk arms can move to different radial distances from the spindle. At each distance, a track is written.

  46. Magnetic Disks

  47. Error-Correcting Codes • Occasional errors may occur in hard disks due to voltage spikes or other causes. • Errors can be handles by adding extra check bits to words of data. Suppose a word has m data bits and r check bits. Let the total length be n = m + r. This n bit unit is often referred to as a codeword. • The number of bits in which two codewords differ is called the Hamming distance.

  48. Error-Correcting Codes • To detectd single-bit errors requires a distance d + 1 code. To correctd single-bit errors requires a distance 2d + 1 code. • Consider a adding a single parity bit to the data. The bit is chosen so that the number of 1 bits in the codeword is even (or odd). Now a single error results in an invalid codeword. It takes two errors to go from one valid codeword to another.

  49. Error-Correcting Codes • Imagine we want to design a code with m data bits and r check bits that will allow all single-bit errors to be corrected. Each of the 2m legal memory words has n illegal codewords at a distance 1 from it. • Form these by inverting each of the n bits in the n-bit codeword. • Each of the 2m legal memory words requires n + 1 bit patterns dedicated to it. • (n + 1) 2m <= 2n since n = m + r, (m + r + 1) <= 2r