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Chapter Six
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Chapter Six

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  1. Chapter Six Pipelining: Datapath & Control

  2. Pipelined datapath • Every piece of data that might be used in a later stage must be stored in a pipeline register. • Sometimes must pass data through several registers before it is used. • Each functional component of the datapath can be used only wihtin a single pipeline stage. • Otherwise get a structural hazard

  3. Pipelined datapath • Bug in load instruction: • Which register is changed in the final stage of the load? • Which instruction supplies the write register number? • The instruction in the IF/ID register supplies the register number, though this instruction occurs after the load instruction! • Must preserve the destination register number in the load instruction. • Must preserve register contents from ID/EX to EX/MEM pipeline register • Must also pass the register number from the ID/EX through EX/MEM to MEM/WB register

  4. Pipelined Datapath Correct version of the datapath: the number used in WB stage to specify the register to be written pass correct portions of the register to each pipeline register

  5. Pipelined Datapath Correct datapath highlighing the hardware used in all 5 stages of the lw instruction

  6. Graphically representing pipelines • Two types of diagrams • Multiple-clock-cycle pipeline diagrams • Single-clock-cycle pipeline diagrams (last series of figures) • Example: lw $10, 20($1) sub $11, $2, $3S • Next slide: multiple-clock-cycle diagram for these. • Time advances left to right • Instructions advance top to bottom. • Representation of the pipeline placed in each portion along the instruction axis. • Following slide: multiple-clock-cycle diagram using the traditional version of naming/drawing

  7. Graphically representing pipelines

  8. Graphically representing pipelines

  9. Graphically representing pipelines • Single-clock-cycle pipeline diagrams • Show state of entire datapath during a single clock cycle • All 5 instructions in pipeline identified by labels above their respective pipeline stages • Shows details of what is happening within the pipeline during each clock cycle • Drawings usually appear in groups to show pipeline operation over a sequence of clock cycles • Example: Lw $10, 20($1) Sub $11, $2, $3

  10. Pipeline control • Label control lines on existing datapath • Borrow from the control for the simple single-cycle datapath • Use same ALU control logic, branch logic, destination-register-number multiplexor and control lines • See figures on following pages for tables describing these signals. • Assumptions: • PC is written on each clock cycle so don’t need control signal • Pipeline registers are written on each clock so don’t need control signals

  11. Pipeline Control: adding control signals

  12. Pipeline Control: ALU control How ALU control bits are set depending on the ALUOp control bits And the different function codes for R-type instructions

  13. Pipeline Control: control signals values

  14. Pipeline control • We have 5 stages. What needs to be controlled in each stage? • Instruction Fetch and PC Increment • Instruction Decode / Register Fetch • Execution • Memory Stage • Write Back • How would control be handled in an automobile plant? • a fancy control center telling everyone what to do? • should we use a finite state machine?

  15. Pipeline control • Instruction fetch • Control signals to read instruction memory and write PC are always asserted. Nothing special to control • Instruction decode/register file read • Same control signals asserted for every instruction. Nothing special to control • Execution/address calculation • Set RegDst (result register) • ALUOp (ALU operation) • ALUSrc(either read data 2 or sign-extended immediate for ALU)

  16. Pipeline control • Memory access • Branch (set by the branch equal instruction) • MemRead (set by load instruction) • set MemWrite (set by store instruction) • PCSrc selects the next sequential address unless control asserts Branch and the ALU result is 0. • Write back • MemtoReg (send ALU result or memory value to register file) • RegWrite (writes the chosen value)

  17. Pipeline control • Pipelining leaves meaning of control lines unchanged. • So use same control values as before • See next slide • Same values as in chapter 5, but grouped by pipeline stage

  18. Pipeline control • Values of the control lines shuffled into three groups corresponding to the last three pipeline stages.

  19. Pipeline control • Must set the 9 control lines to these values in each stage for each instruction • Simplest method: extend pipeline registers to include control information. • Create control information during instruction decode stage. Signals move down the pipeline registers. • Use the control information during appropriate stage • See next slide for control movement • See following slide for final datapath with extended pipeline registers and control signals connected to the proper stage.

  20. Pipeline control

  21. Pipeline control

  22. Pipeline control: example Lw $10, 20($1) Sub $11, $2, $3 And $12, $4, $5 Or $13, $6, $7 Add $14, $8, $9 • Note the sequence of the destination register numbers from left to right at the bottom of the pipeline registers. • When a stage is inactive, the values of the control lines that are deasserted are shown as 0 or X • Sequencing control is embedded in the pipeline structure itself. • All instructions take same number of clock cycles • All control information is computed during instruction decode then passed along

  23. Pipeline control: example

  24. Pipeline control: example

  25. Pipeline control: example

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  27. Pipeline control: example

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  29. Pipeline control: example

  30. Pipeline control: example

  31. Pipeline control: example