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Low Power Front End for the Optical Module of a Neutrino Underwater Telescope

Low Power Front End for the Optical Module of a Neutrino Underwater Telescope. D. Lo Presti University of Catania -Microelectronics Group University of Bologna - Electronics Group. Summary. Front end electronics for a Km 3 submarine neutrino detector: LIRA chip

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Low Power Front End for the Optical Module of a Neutrino Underwater Telescope

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  1. RD07 Florence-June 27-29, 2007 Low Power Front End for the Optical Module of a Neutrino Underwater Telescope D. Lo Presti University of Catania -Microelectronics Group University of Bologna - Electronics Group

  2. RD07 Florence-June 27-29, 2007 Summary • Front end electronics for a Km3 submarine neutrino detector: • LIRA chip • Test of the first prototype of the Front-end using LIRA chip ( CT-BO ) see F. Giorgi talk • Study and design of the new front-end • Specifications • Architecture • Status of work

  3. RD07 Florence-June 27-29, 2007 LIRA01 and LIRA02 Not Submitted to foundry LIRA03 LIRA04 LIRA05 AMS 0,35 mm CMOS Technology Europractice MPW LIRA Chip

  4. RD07 Florence-June 27-29, 2007 Trigger and Single Photon Classifier TSPC PLL Stand Alone 400 MHz Slave Clock Generator LIRA’s PLL Shielded Mixed Digital Analogue Mixed Digital Analogue Pure Analogue 2 AM 200 MHz Write 10 MHz Read LIRA05 CHIP CMOS 0,35 mm AMS technology

  5. RD07 Florence-June 27-29, 2007 LIRA Chip • 2 SCA 3 ch.x256 cells working alternatively in read and write mode to reduce dead time • 200 MHz sampling 10 MHz transfer • 9 bit resolution • Anode and last dynode sampled (double linear dynamic) • 20 MHz master clock sampled for time stamp • Trigger and Single Photon Classifier • 3 5-bit DAC with slow control interface • PLL to produce 200 MHz on chip • 120 mW total power dissipation!!

  6. RD07 Florence-June 27-29, 2007 FPGA Spartan 3E Socket chip LIRA Front end using LIRA chip ANALOG Mezzanine di debug DIGITAL See F. Giorgi talk

  7. RD07 Florence-June 27-29, 2007 Simulations • High energy neutrino events in NEMO detector • 40K spe background • Seawater Optical properties • Optical module spacing, orientation and position • Hits in each pmt of the detector in presence of an event

  8. RD07 Florence-June 27-29, 2007 22 PMT 440 PMT 216 PMT Event n° 290. Intervals between first and last pulse p.e. p.e. p.e. Event n° 362. Intervals between first and last pulse 50 100 40 80 Event n° 015. Intervals between first and last pulse 25 20 22 PMT 440 PMT 216 PMT 15 60 30 10 5 20 40 0 0 20 40 60 80 100 120 time (ns) 20 10 0 0 0 500 1000 1500 2000 -1000 0 1000 2000 3000 4000 5000 time (ns) time (ns) Event n° 015. Photoelectrons from photocatodes Event n° 290. Photoelectrons from photocatodes 20 Event n° 362. Photoelectrons from photocatodes 200 350 300 15 150 250 10 200 100 150 5 100 50 50 0 1 1.5 2 2.5 3 3.5 4 0 0 0 500 1000 1500 2000 2500 0 5000 10000 15000 Charge Dynamics p.e. spectra of three typical high energy neutrino events Need for several input dynamics Time Dynamics Maximum signals length spectra of three typical high energy events Specialized Samplers

  9. RD07 Florence-June 27-29, 2007 Study and Design of the Front-End Electronics • Simulation of neutrino events in a realistic detector (NEMO like) • Simulation of the real Optical Module response • Optimal Signal Filtering • Simulation of the Front-End chain with realistic performances • Evaluation of the detector performances as regards to acquisition parameters • Considerations on Power Dissipation and data flow • ASIC design

  10. RD07 Florence-June 27-29, 2007 Filtered PMT Signal

  11. RD07 Florence-June 27-29, 2007 40K Rate vs Readout frequency 30kHz 50kHz 500kHz 2 ns 50 ps Dead time vs. ADC freq. 100 ps We must use a buffer solution to limit dead time. A p.e. signal is long less than 40 ns. At 200Msample/sec we will use 10 cell blocks. We have simulated dead time vs block number for different 40K rates. Four 10-cell block are able to limit dead time at reasonable dead time

  12. RD07 Florence-June 27-29, 2007 10 p.e. OutB OutA OutC

  13. RD07 Florence-June 27-29, 2007 W Z , 300 W C , 5ns; j , 100ps ; Z , 300 ; S , 1V; P , 1.5mV ; ADC, 10 bit L o a d k t r m s L o a d p a n e d r m s 3 10 160 r d 3 150 140 2 10 n d s 2 m 130 r , ps Channel dynamics 120 t s direct 1 10 110 100 0 10 90 6 7 8 0 10 20 30 40 50 60 10 10 10 6 G G (x10 ) p m t p m t 0.7 0 10 20 30 40 50 60 10 p.e. W Z , 300 L o a d 4 10 10 photoelectrons Tipical amplitude (mV) 3 10 2 10 6 7 8 10 10 10 Gpmt=8.106 G p m t W W C , 5ns; j , 100ps ; Z , 300 ; S , 1V; P , 1.5mV ; ADC, 10 bit C , 5ns; j , 100ps ; Z , 300 ; S , 1V; P , 1.5mV ; ADC, 10 bit k t r m s L o a d p a n e d r m s k t r m s L o a d p a n e d r m s 1.4 -0.51 1.3 -0.515 1.2 -0.52 1.1 -0.525 , % systematic error, p.e. 1 -0.53 q s 0.9 -0.535 0.8 -0.54 -0.545 -0.55 0 10 20 30 40 50 60 6 6 G (x10 ) G (x10 ) p m t p m t

  14. RD07 Florence-June 27-29, 2007

  15. RD07 Florence-June 27-29, 2007 FADC 20 MHz 10 bit FADC 20 MHz 10 bit Optical Module Low Power Front-end Architecture Serial Ctrl Slow Control Data Pack & Transfer Unit Ext. Interface OM Connector FPGA Control Unit HV Control Monitor MasterClock CTRL +Data FIFO Class. Serial Ctrl PMT Interface T&SPC Cust. EL. FPGA Class. Code ASIC MUX OUT Class. CTRL +Data G1 G2 G3 60ns X10 PLL Anode SAS chip Control Unit 60ns IN 60ns Integrator

  16. RD07 Florence-June 27-29, 2007 Ra Rb PMT Interface TSPC 30 ns Delay lines PMT Interface Block Diagram 3MHz @ -3dB 10MHz @ -60dB Protection -1 Filter Integrator Pd 80 mW x1 Protection -1 x4 OUT A Filter Delay R1 /8 -1 OUT B x4 Protection Filter Delay Rtot = 300W R2 /64 OUT B x4 Protection -1 Filter Delay R3 30MHz@ -3dB 100MHz@ -60dB IC Delay Line 30 ns

  17. RD07 Florence-June 27-29, 2007 PMT interface - measurements < 8 pe 8 pe ÷ 64 pe Integrator 64 pe ÷ 512 pe > 512 pe

  18. RD07 Florence-June 27-29, 2007 x1 Limitazione x1/8 x1/64 PMT interface - linearity Test with 100mV ÷ 8,56 V equivalent to anode current pulse 333uA ÷ 28mA -> @ range 3pe ÷ 280 pe (5*106, 300W) PMT saturation @ 1nC = about 1250 pe (5*106, 300W)

  19. RD07 Florence-June 27-29, 2007 PMT dynamic range VS Gain The effect of saturation seems to be determined by the anodic pulsed current and independent from the gain. Limit Value of about 1 nC 120-150 p.e. @ gain 5·107 nVs @ gain 5·107 nVs @ gain 1·107 nVs @ gain 5·106 Fit of first 5 pts nVs Number of photoelectrons

  20. RD07 Florence-June 27-29, 2007 Trigger & Single Photon Classifierblock diagram Out C B2 • B0, B1, B2 = PMT signal classification code • SOT, Signal Over Threshold, twofold use: • Rising edge Trigger; • SOT width determines sampling mode (Short, Long, Integ.) • Th0 e Th1 generated by 2 6-bit DAC serial code (Slow Control). • Th0 trigger threshold; • Th1 Out of range threshold. • Asynchronous and always active. Out B B1 Out A B0 Th1 SOT Th0 Fast comparator with hysteresis

  21. RD07 Florence-June 27-29, 2007 t0 t1 Th1 Out A Th0 Out B From PMT Out C From PMT Interface An example… • @ t0 event trigger; • Dt= t1 –t0 compared to Short • length (60 ns); • If bigger after a Short also a Long sampling of the signal. • The classification code is: • B0=1; B1=0; B2=0. • OutB samples will be converted!! Th1 Th1

  22. RD07 Florence-June 27-29, 2007 b0,b1,b2,SOT from TSPC 3x128 Out A 3x16 Out B 3x16 Out C 3x16 3x16 3x16 CHIP SAS - block diagram (Smart Autotriggering Sampler)

  23. RD07 Florence-June 27-29, 2007 Sampling • 3 sampling modes: • SAS_SHORT • 4 independent memory banks: sampling @ START (T&SPC) • 3 channels 16 cells • 200 MHz sampling 20 MHz transfer • Serial transfer towards ADC • SAS_LONG • T&SPC enabled: signal over Threshold more than 60 ns • 3 channels 128 cells • 200 MHz sampling 20 MHz transfer • Serial transfer towards ADC • FADC (external 10b 20 MHz ADC) • T&SPC enabled: signal over Threshold more than 640ns • Integrated signal • 10 bit 20 MHz Flash ADC • 1 Ksample record length

  24. RD07 Florence-June 27-29, 2007 Time Stamp Mechanism Anode signal [V] Interpolation to samples Threshold T&SPC Time stamp 4 bit counter 16 bit counter Time (ns) • Time Stamp = 20 bit sent to data acquisition • One time stamp for sampler • Dedicated FIFO • t0 reconstructed offline

  25. RD07 Florence-June 27-29, 2007 total 1602 p.e. 250 700 p.e. meas. 1389 600 200 500 150 400 p.e. 300 100 200 50 100 0 0 0 500 1000 1500 0 500 1000 Time [ns] Ch1 = 12 p.e. Ch1 = 70 p.e. Ch1 = 400 p.e. s p a n s p a n s p a n 12 70 400 60 10 300 50 8 40 6 200 p.e. p.e. p.e. 30 4 20 100 2 10 0 0 0 0 500 1000 0 500 1000 0 500 1000 Time [ns] Time [ns] Time [ns] Event 362. PMT 364. SCA 1 D Q/Q = 0.5 % 1600 FWHM = 167.5 ns Max 677 p.e. 1400 p.e meas. 1610 1200 1000 20 MHz ADC input 800 600 400 200 Gpmt=8.106 ZL=300W 0 0.2 0.4 0.6 ms Time [ns] Time [ ]

  26. RD07 Florence-June 27-29, 2007 Very rare event -> 5 successive pulses @ more than 50 ns 4 events fully sampled– 1 lost Gpmt=8.106; ZL=300W Structured signal -> well reconstructed with 128 cells

  27. RD07 Florence-June 27-29, 2007 ADC SCA In this event we have 13097 p.e. We are able to measure its charge using a 128 SCA (640ns) with an error < 0.26% Gpmt=8.106; ZL=300W 690 ns

  28. RD07 Florence-June 27-29, 2007 Conclusions • The front end electronics architecture has been defined and under design; • PMT interface and TSPC ready; • Master Control Unit (FPGA) ready; • See F. Giorgi talk • ASIC ready soon (beginning of 2008); • Test in NEMO phase 2

  29. RD07 Florence-June 27-29, 2007 Thank You

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