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Optimized design of a back-to-back NPC converter to be used as interface of renewable energies

Optimized design of a back-to-back NPC converter to be used as interface of renewable energies. Emilio J. Bueno 1) , Santiago Cobreces 2) , Francisco J. Rodríguez 3) , Álvaro Hernández 4) , Felipe Espinosa 5) , Raúl Mateos 6) , Juan C. García 7) , Félix López 8). Contents.

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Optimized design of a back-to-back NPC converter to be used as interface of renewable energies

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  1. Optimized design of a back-to-back NPC converter to be used as interface of renewable energies Emilio J. Bueno1), Santiago Cobreces2), Francisco J. Rodríguez3), Álvaro Hernández4), Felipe Espinosa5), Raúl Mateos6), Juan C. García7), Félix López8)

  2. Contents • Introduction. • Power Electronics System. • Control Electronics System. • Practical results. • Summary.

  3. VSC1 VSC2 P 3*L1 3*L2 Motor Line impedance CDC Distribution line Disturbances … 3*Co N Problems to solve in the connection of VSCs to the grid (1/2) from the converter towards the grid: • PWM commutations. Can be reduced using a LCL-filter and a mutilevel converter. • Temporal drifts of the filter components. • Inductances saturation. from the grid towards the converter: • Unknown line impedance (weak grid). • Line voltage harmonics. • Permanent unbalanced line voltages. • Temporal unbalanced line voltages (dips).

  4. VSC2 P VSC1 Sa2 Sc2 Sb2 Sa2 Sb2 Sc2 CDC2 Db2 Dc2 Da2 Db2 Da2 Dc2 3*L2 3*L1 Sa1 Sc1 ea Sb1 Sa1 Sb1 Sc1 eb AC Motor n NP ec Da1 PCC Da1 Db1 Dc1 Db1 Dc1 3*Co Sa2 Sb2 Sc2 Sa2 Sc2 Sb2 CDC1 Sa1 Sb1 Sa1 Sc1 Sc1 Sb1 N “CONDOR” project (1/2) • CONDOR: “Double converter based on multilevel inverters designed for recovering energy and minimizing electromagnetic emissions”. • Financed by the Spanish Science and Technology Ministry (DPI2002-04555-C04). • Duration: December, 2002 – December, 2005. • Researching groups: University of Alcalá (Coordinator), University of Carlos III, University of Valencia and Institute for Electrical Technology of Valencia. • Collaborating companies: SEDECAL CONTROL.

  5. Auxiliar breaker P VSC1 VSC2 3*L1 3*L2 ea PCC CDC2 eb NP AC motor n CDC1 Power Electronics System ec Main breaker 3*Co N Auxiliar rectifier “CONDOR” project (2/2) Control Electronics System ADCs Measurements of DC-bus variables ADCs Measurements of motor variables ADCs Measurements of grid filter variables PWM VSC 1 PWM VSC 2 FPGA SPARTAN 2E Interface card between the Coprocessor Module – Power Electronics System Communication card Coprocessor Module VSC 1 Control VSC 2 Control References References DSP TMS6713

  6. Objectives • This work presents the construction of the Power Electronics System, the converter limitations to compensate unbalanced dips, and the designs of grid filter components and DC-bus capacitors. • In this work the grid filter is the LCL and the analytical equations for the components are obtained to verify the ICE 61000-3-4 standard. • As for the DC-bus capacitors, the analytical equations for the ripples in uDC due to iDC and iNP are obtained. From these equations, the DC-bus capacitors are calculated. • With respect to the Control Electronics System, the chosen structure and the task distribution between the system processors are presented.

  7. Contents • Introduction. • Power Electronics System. • Control Electronics System. • Practical results. • Summary.

  8. Specifications of the utility grid and the converter Power electronics specifications and assembly

  9. Converter limitations to compensate unbalanced dips • The maximum peak phase current to compensate the unbalanced voltage dips and with zero phase jump can be calculated approximately as: • The system must be oversized to compensate voltage dips to nominal power. The elements that limit this current are mainly the grid filter inductances and the IGBT’s. • If the excess energy is not stored or dissipated the DC-bus voltage increases. The elements that determine the DC-bus voltage limitations are the IGBTs (maximum direct collector emitter voltage) and the DC-bus capacitors (nominal voltage).

  10. The design expressions are • Co is the 5% of Cbase. • Capacitor. i1 in function of Co is: Grid filter design Filter limitations • Resonance frequency. • Inductance. The total value of the inductances should not be bigger than 10% of Lbase. Chosen values are • L1=0.5mH/175Arms. • L2=0.25mH/150Arms. • Co=100μF/400Vrms.

  11. Ripple due to iDC Ripple due to iNP Calculation of the DC-bus capacitors Simplified diagram of a back-to-back converter based on two NPC’s

  12. Contents • Introduction. • Power Electronics System. • Control Electronics System. • Practical results. • Summary.

  13. Control electronics system (1/3)

  14. Control electronics system (2/3) Control Electronics System ADCs Measurements of DC-bus variables ADCs Measurements of motor variables ADCs Measurements of grid filter variables PWM VSC 1 PWM VSC 2 FPGA SPARTAN 2E Interface card between the Coprocessor Module – Power Electronics System Communication card Coprocessor Module VSC 1 Control VSC 2 Control References References DSP TMS6713

  15. Control electronics system (2/2)

  16. Contents • Introduction. • Power Electronics System. • Control Electronics System. • Practical results. • Summary.

  17. “CONDOR” project (2/2)

  18. Ripple due to iDC Ripple due to iNP Some converter waveforms VSC1 working as non controlled rectifier and VCS2 driving to induction machine

  19. Controller programming Start main() and init_system() No t(k)=k·TS=k·200μs Yes → c_int(5) Any hardware fault? Data acquisition Yes → c_int(4) + Yes Any fault? + No acquisition_data() System protection system_protection() Output controller reference_PWM() Stop PI SPLL spll_pi() DSC dsc() • TMS320C6713 DSP is operating at 225MHz. • Cycle clock is 4.44ns. • Sampling time is 200μs • The execution average time of the Control algorithm is 32μs. DC_bus controller dcbuscontroller() c_int(5) Control algorithm Current controller currentcontroller()

  20. Contents • Introduction. • Power Electronics System. • Control Electronics System. • Practical results. • Summary.

  21. Summary • A back-to-back NPC three-level converter of 100KVA has been designed, validated by simulation and tested in a real converter. • In the “Power Electronics System”: (1) the converter limitations to compensate voltage dips have been analysed; (2) a method for designing the grid filter components has been proposed; and (3) the factors that determine the DC-bus capacitor values have been analysed. • With respect to the “Control Electronics System”, the chosen structure and the task distribution between the two processors have been presented.

  22. Thank you for your attention!!! Emilio J. Bueno1), Santiago Cobreces2), Francisco J. Rodríguez3), Álvaro Hernández4), Felipe Espinosa5), Raúl Mateos6), Juan C. García7), Félix López8) Acknowledgment: This work has been financed by the Spanish administration (CICYT: DPI2002-04555-C04-04).

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