1 / 34

CMOS Analog Integrated Circuits: Models, Analysis, & Design

CMOS Analog Integrated Circuits: Models, Analysis, & Design. Dr. John Choma, Jr. Professor of Electrical Engineering University of Southern California Department of Electrical Engineering-Electrophysics University Park; Mail Code: 0271

soren
Télécharger la présentation

CMOS Analog Integrated Circuits: Models, Analysis, & Design

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CMOS Analog Integrated Circuits: Models, Analysis, & Design Dr. John Choma, Jr. Professor of Electrical Engineering University of Southern California Department of Electrical Engineering-Electrophysics University Park; Mail Code: 0271 Los Angeles, California 90089-0271 213-740-4692 [OFF] 626-915-7503 [HOME] 626-915-0944 [FAX] johnc@almaak.usc.edu (E-MAIL) EE448 MOS Circuit Level Models Fall 2001

  2. Static Model • Cutoff Region • Ohmic (Triode) Region Model • Saturation Region Model • Subthreshold Model • Short Channel Effects In Saturation • Channel Length Modulation • Substrate/Bulk Phenomena • Mobility Degradation • Carrier Velocity Saturation • Small Signal Model In Saturation • Forward Transconductance • Bulk Transconductance • Capacitances • Sample Circuit Analysis (Inverter) • Gain • Bandwidth Lecture Overview 2

  3. L L L d d S G D Silicon Dioxide T D ox   I d V gd I I  g Drain b N+ N+ V X G B Source ds d   W V V gs I bs s    P–Type Substrate S (Concentration = ND cm-3 ) B I = I + I + I s d g b I  0 g I  0, for V < 0 b bs I  I s d V = V – V ds gs g d N–Channel MOSFET 3

  4. L L L d d S G D Silicon Dioxide T ox P+ Drain Source P+ X d W N–Type Substrate (Concentration = ND cm-3 ) B I = I + I + I s d g b D   I I  0 V d g dg I I  g b V G B I  0, for V < 0 sd b sb   V V I  I sg I sb s s d    S V = V – V sd sg d g P–Channel MOSFET 4

  5. V hn V  V V < V – V gs hn ds gs hn  µ n ox K = µ C = n n ox T ox / 3 2 T o µ(T)  µ(To) T V – V – V   I I I 1 gs hn ds d W d d  = K V – V – V = n gs hn ds  R L V V V V ds ds ds ds ds V – V – gs hn 2 • l Cutoff Regime: • Threshold Voltage, Function Of Bulk–Source Voltage • l Ohmic Regime: • (Hundreds Of µmhos/Volt) • l Comments • W/L Is Gate–Channel Aspect Ratio, A Designable Parameter • Temperature Effects (Holes And Electrons): • Resistance For Small Drain–Source Voltage: Characteristic Curves: Cutoff And Ohmic Regimes  and 5

  6. V  V & V  V – V gs hn ds gs hn V V – V dss gs hn K W 2 n I = V dss dss 2 L • l Saturation Regime: • l Comments • Square Law Voltage–Controlled Current Source • Drain Current Shows Negative Temperature Coefficient • Because Of Its Proportionality To Mobility • Differential Current Of Two Matched Devices Is Linear With • Differential Gate–Source Voltage , Provided Common Mode • Gate–Source Voltage Is A Constant Characteristic Curves: Saturated Regime   Drain Saturation Voltage  Drain Saturation Current 6

  7. l Inputs Simple Differential Pair l Response lNote Differential Output Current And Voltage Are Linear With Respect To Differential Input Voltage Without Invoking Small Signal Approximation 6a

  8. 2 n V W / ( V – V ) n V T e I = 2 K gs hn T  d n L Characteristic Curves: Subthreshold Regime l Subthreshold Regime: s s s l Comments s Bipolar Type I–V Action Indigenous To Subthreshold Regime s Subthreshold Operation Corresponds To Gate–Channel Interface Potentials Lying Between One And Two Fermi Potentials s Useful Only For Low Speed, Low Power Applications 7

  9. Sample Simplified MOS Static Characteristics 8

  10. V ds   S D l Depletion l Zero Current l lVoltage Across Oxide lInterface Potential V gs   V  0 c SiO G ds I 2 d 0 < V < V gs hn V  0 bs              Fixed Immobile N+ Drain Source Charges N+ DEPLETION LAYER, V  0 ds V  ox DEPLETION LAYER, V = 0 ds  V P–Type Substrate y V   bs B Cutoff Regime 9

  11. G S D N+ N+ Drain Source P–Type Substrate L G S D V > V gs hn N+ N+ Drain 0  V  V – V Source ds gs hn V > V gd hn  V   D V  dss ds L ' D L P–Type Substrate Metal or Polysilicon Inversion Layer Silicon Dioxide Depletion Channel Inversion: Ohmic Regime 10

  12. G S D V > V N+ gs hn N+ Drain Source 0  V = V – V ds gs hn P–Type Substrate V  V gd hn L G S D V > V gs hn N+ N+ 0  V > V – V Drain ds gs hn Source V < V gd hn  V    V  dss ds L '  L P–Type Substrate Metal or Polysilicon Inversion Layer Silicon Dioxide Depletion Channel Inversion: Saturation Regime 11

  13. G S D N+ N+ Drain Source  V    V  dss ds L ' D L K V – V L W 2 n ds dss I = I = V – V 1 + d dss gs hn |  L 2 L V  V > V ds dss 2 q N A V = L V – V + V  ds dss j  s Channel Length Modulation l Modified Saturation Regime Current L – l Channel Modulation Voltage (Typically Under 20 Volts And As Small As 1/3 Volt For Deep Submicron MOSFETs) 12

  14. K V – V L W 2 n ds dss I = I = V – V 1 + d dss gs hn |  L 2 L V  V > V ds dss 2 q N A V = L V – V + V  ds dss j  s l Modified Saturation Regime Current Channel Length Modulation Parameters L – • l Parameters •  Average Substrate Impurity Concentration •  Dielectric Constant Of Silicon (1.05 pF/cm) •  Electronic Charge Magnitude •  Channel Length Modulation Voltage •  Built In Substrate–Drain/Source Junction Potential • l Note • Large Channel Length Reduces Channel Modulation • Small Substrate Concentration Increases Channel Modulation 13

  15. K V – V W 2 n ds dss I = V – V 1 + d gs hnc 2 L V  V bs V = V + 2 V V – V 1 – – 1  h ho F T 2 V – V F T 2  q N T A s  ox V = = q N   A s 2 C ox ox l Effect On Threshold Voltage Substrate/Bulk Phenomena • (High Hundreds Of µVolts) • (Few Tenths Of Volts) • l Parameters •  Fermi Potential; Renders Channel Surface Intrinsic •  Intrinsic Carrier Concentration In Substrate •  Dielectric Constant Of Silicon Dioxide (345 fF/cm) • l Note • Small Oxide Thickness Reduces Threshold Modulation • Small Substrate Concentration Reduces Threshold Modulation  ox 14

  16. Threshold Correction (volts) Threshold Voltage Modulation Bulk–Source Voltage, Vbs (volts) 15

  17. µ n µ neff V – V gs hnc 1 + V E 6 V (500)(10 T E ox Mobility Degradation Due To Vertical Field • l Electric Field Problems • Thin Oxide Layers Conduce Large Gate -To- Channel Fields • For Even Small -To- Moderate Gate–Source Voltages • These Enhanced Fields Impart Increasing Energies To Carriers, • Thereby Causing More Carrier Collisions And Degraded Mobilities • l Mobility: • l Parameters •  Effective Carrier Mobility In Channel •  Vertical Field Degradation Voltage Parameter • Crude One Dimension Approximation To Two Dimensional Problem • in MKS Units Yields In Volts  (Low Hundreds Of Volts)  ) 16

  18. K = µ C K = µ C n n ox neff neff ox V – V 2 ds dss V – V 1 + gs hnc K V W  n I = d 2 L V – V gs hnc 1 + V E Impact Of Mobility Degradation • l Static Drain Current • l Other Effects • Reduced Bandwidth And Increased Carrier Transit Time • Smaller Current For Given Gate–Source Bias • Reduced Forward Transconductance  17

  19. µ v n sat µ = ne E E + E h c h 1 + E c µ E n h v = µ E ne h E h 1 + E c V – V gs hn E  h L • l Electric Field Problems • Short Channels Conduce Large Drain -To- Source Fields • For Even Small -To- Moderate Drain–Source Voltages • These Enhanced Fields Impart Increasing Energies To Carriers, • Thereby Causing More Carrier Collisions And Degraded Mobilities • At Very Large Horizontal Fields, Carrier Velocities Ultimately • Saturate To A Value Of , Which Is About 0.1 µm/pSEC • Saturation Occurs When Horizontal Field, ,Equals Or Exceeds A • Critical Value, , Which Is About 5 V/µm • l Mobility And Field Mobility Degradation Due To Lateral Field   18

  20. Velocity – Mobility – Field Relationships Carrier Velocity (µm/psec) Normalized Carrier Mobility 0.1 1 0.09 0.9 Carrier Velocity 0.08 0.8 0.07 0.7 0.06 0.6 0.05 0.5 0.04 0.4 Normalized Mobility 0.03 0.3 0.02 0.2 0.01 0.1 0 0 0 5 10 15 20 25 30 35 40 45 50 Lateral Electric Field (V/µm) 18a

  21. µ µ µ n n n µ   = ne E V – V V h gs hnc dss 1 + 1 + 1 + E L E L E c c c V – V V gs hnc dss E  = h L L V  Mobility And Lateral Field • l Mobility And Field • l Electric Field Problems • Crude Approximation For Horizontal Field, • Free Carriers Exist Only Over Channel Where Voltage With • Respect To The Source Is At Most • Channel Length, L, Should Be Effective Channel Length, L', • But This Shrinkage Is Already Accounted For By Channel Length • Modulation Voltage Parameter, • Is About 1.75 Volts For L = 0.35 µm 19

  22. K = µ C K = µ C n n ox neff neff ox V – V 2 ds dss (V – V ) 1 + gs hnc K V W  n I = 2 L V – V gs hnc 1 + L E c W C v V – V ox sat ds dss I V – V 1 + d gs hnc 2 V l Volt–Ampere Impact Of High Lateral Field • l Static Drain Current • l Very High Fields • l Comments • Drain Current Scales Approximately With W, As Opposed • To W/L • Drain Current Almost Linear W/R To Gate–Source Voltage  d  20

  23. MOS Large Signal Model  Gate-Drain Capacitance  Gate-Source Capacitance Static Drain Current  Drain-Bulk Capacitance  Source-Bulk Capacitance  Drain Overlap Capacitance  Source Overlap Capacitance  Drain Ohmic Resistance  Source Ohmic Resistance  Bulk Ohmic Resistance  Bulk Spreading Resistance DBD Bulk-Drain Diode  Bulk Spreading Resistance DBS Bulk-Source Diode 21

  24. C + C C = W L C gd old old d ox  Device Capacitances In Saturation  Drain-Bulk Junction Area  Large (Hundreds Of fF)  Source-Bulk Junction Area  Large (Hundreds Of fF)  Zero Bias Depletion Capacitance Density  Moderate (High Tens Of fF)  Small (Tens Of fF) 22

  25. I W d g 2 K I D mf n dQ L  V | gs Q  I d g =  g mb b mf  V | bs g v g v mf ga mb ba Q / V 2   = b 2 V – V – V G F T bsQ I  I dQ d g o V + V – V  V |  ds dss ds Q B C old Approximate (Long Channel) Small Signal Model   c C C gd db c c c c  g o C C gs sb c c c c c v v   + + ga ba C   ols c S • l Assumptions • All Series Ohmic Resistances Are Negligible • Transistor Operates In Saturation Regime • "Long Channel" Approximation Invoked For Static Drain Current • Model To Be Used As A Precursor To Computer–Based Studies 23

  26. V – V 2 ds dss V – V 1 + gs hnc K V W  n I = d 2 L V – V gs hnc 1 + L E c V – V ds dss f =  V  / V 2   = b 2 V – V – V F T bsQ / / 1 + f V 2 V f 2   dss c g = g 1 – – mfs mf 1 + f 1 + f 1 + f c  c g =  g mbs b mfs I dQ g = o V + V – V  ds dss Short Channel Small Signal Model l Drain Current: l Intermediate Parameters: l Forward Transconductance: l Bulk Transconductance: l Output Conductance: 24

  27. s  ox Hypothetical Device l Physical Parameters l Device Parameters = 1.05 pF/cm = 345 fF/cm l Circuit Parameters 25

  28. V  V hnc hn V  K = 276.0 µmho / volt n f  l Peripheral Calculations Static Performance  = 685.2 mV (Compensated Threshold) = 35.2 mV = 669.7 mV (Channel Length Voltage) (Transconductance Parameter) = 2.218 (Channel Length Parameter) • l Static Drain Current • Note Short Channel -To- Long Channel Ratio of 2.35; Ratio Is • Generally Between 1.5 And 3.0 26

  29. –3  = 5.0 2 (10) (Bulk Parameter) b • l Forward Transconductance • Note Short Channel -To- Long Channel Ratio of 1.14; Ratio Is • Generally Between 0.5 And 2.0 • l Bulk Transconductance • Note Bulk Transconductance Is About 200 Times Smaller • Than Forward Transconductance • l Drain–Source Conductance • Corresponds To Shunt Output Resistance Of About 5 K • Mandates Conductance Enhancement Strategies When • Designing High Performance Transconductors Small Signal Parameters 27

  30. D V C + C dd gd old c c c I C big bias g i g v g v o out c mf 1 mb 2 c c c C + C gs ols i i i in out in c v v   + + G S B 1 2 g – s C + C i mf gd old out = i s C + C + C + C in gs ols gd old µ V – V g n gs hn mf  T C + C + C + C 3 L 2 2 gs ols gd old d L + 3 L <<  C g T gd mf AC Short Circuit Device Unity Gain Frequency l   l • l Comments • Unity Gain Frequency Is Good Device Figure Of Merit; • Crude Circuit Performance Figure Of Merit • Result Assumes 28

  31. Common Source Inverter 29

  32. V r + r 1 x ddl ol R = r + Leff ssl I 1 + 1 +  g r 1 +  g x bl mfl ol bl mfl Inverter Load Resistance Calculations   30

  33. V g R g os mfd Leff mfd A = g R v mfd Leff  V R + r + r 1 + g s Leff ddd ssd bl mfl  1 + 1 + g r + bd mfd ssd r od / W L 1 d A v 1 +  / W L bl l Inverter Gain Calculations = –  –  –  – 31

  34. 1 1 1 B = = 3dB R C R C / | R R C out L Leff L Leff L V / x R = = r + r + 1 + 1 +  g r r ddd ssd bl mfd ssd od I x 1 +  g g 1 bl mfl mfd B A B = 3dB v 3dB R C C C Leff L L L Inverter Bandwidth Calculations    GBP  32

More Related