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EECE 374: Microprocessor Architecture and Applications Spring 2011

EECE 374: Microprocessor Architecture and Applications Spring 2011. Microprocessor. What is it?. (Program Control Unit). (Data Processing Unit). Microprocessor. What is it? What is the function of control, data path, memory, and input/output? A minimum set of functions in microprocessor

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EECE 374: Microprocessor Architecture and Applications Spring 2011

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  1. EECE 374: Microprocessor Architecture and ApplicationsSpring 2011

  2. Microprocessor • What is it? (Program Control Unit) (Data Processing Unit)

  3. Microprocessor • What is it? • What is the function of control, data path, memory, and input/output? • A minimum set of functions in microprocessor • Control: (un)conditional branch • Data path: addition of two numbers • Results: sum and status (e.g., zero, over/underflow) • Memory: read and write • Data is located with an address • Input/output

  4. A Minimum Microprocessor Binary format My first program 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 01 00 00000101 01 10100000 10 01110110 11 00010000 *R1 is assumed to be initialized to zero =

  5. A Minimum Microprocessor Memory My first program LD R2 00, i.e., b10100000 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 10 PC Control decode + branch Data path adder Registers R1,R2,R3 0 Zero *PC = program counter

  6. A Minimum Microprocessor Memory My first program Data at 00, i.e., b00000101 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 10 PC Control decode + branch Data path adder Registers R1,R2,R3 5 Zero

  7. A Minimum Microprocessor Memory My first program 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 10 Control decode + branch Data path adder Registers R1,R2,R3 PC 5 Zero 0 if the result is zero Zero = 1 else Zero = 0

  8. A Minimum Microprocessor Memory My first program 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 10 Control decode + branch Data path adder Registers R1,R2,R3 PC Zero PC = 10 since Zero!=1

  9. A Minimum Microprocessor Memory My first program LD R2 00, i.e., b10100000 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 10 PC Control decode + branch Data path adder Registers R1,R2,R3 Zero We restart at 01 We do the same thing, R3=R1+R2=0+5 over and over again!

  10. A Minimum Microprocessor We need to increase the size of this field My first program! 00 5 01 LD R2 00 10 ADD R3 R1 R2 11 BRNZ 01 Too small code size! What if 4 bit address instead of 2 bits?

  11. A Minimum Microprocessor My first program! 0000 5 0001 LD R2 0000 0010 ADD R3 R1 R2 0011 BRNZ 0001 Let’s change my program to do something meaningful!

  12. A Meaningful Example Assumption R0 is initialized to 0 Assumption 1 int = 1 byte 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 int a = 1; //  R1 int n = 5; //  R2 int d = -1; //  R3 int r = 0; //  R0 while(n!=0) { // BRNZ r = r + a; // R0=R0+R1 n = n + d; // R2=R2+R3 } Compiler!

  13. A Minimum Microprocessor Memory My first program LD R1 0000, i.e., b10 0001 0000 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 PC 0 1 Zero

  14. A Minimum Microprocessor Memory My first program LD R2 0001, i.e., b10 0010 0001 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 0 1 5 PC Zero

  15. A Minimum Microprocessor Memory My first program LD R3 0010, i.e., b10 0011 0010 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 0 1 5 -1 Zero PC

  16. A Minimum Microprocessor Memory My first program ADD R0 R0 R1, i.e., b01 0000 0001 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 1 1 5 -1 Zero PC

  17. A Minimum Microprocessor Memory My first program ADD R0 R0 R1, i.e., b01 0000 0001 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 1 1 4 -1 Zero 0 PC

  18. A Minimum Microprocessor Memory My first program BRNZ 0111, i.e., b00 0111 0000 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 1 1 4 -1 Zero 0 PC = 0111 since Zero != 1 PC

  19. A Minimum Microprocessor Memory My first program ADD R0 R0 R1, i.e., b01 0000 0001 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 2 1 4 -1 Zero 0 PC

  20. A Minimum Microprocessor Memory My first program ADD R0 R0 R1, i.e., b01 0000 0001 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 2 1 3 -1 Zero 0 PC

  21. A Minimum Microprocessor Memory My first program BRNZ 0111, i.e., b00 0111 0000 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 5 1 0 -1 Zero 1 PC After three more iterations …

  22. A Minimum Microprocessor Memory My first program BRNZ 0111, i.e., b00 0111 0000 0000 1 0001 5 // # iterations 0010 -1 0011 XX // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 5 1 0 -1 Zero 1 PC = 1010 since Zero=1 PC

  23. A Minimum Microprocessor Memory My first program ST R0 0011, i.e., b11 0011 0000 0000 1 0001 5 // # iterations 0010 -1 0011 5 // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Control decode + branch Data path adder Registers R0,R1,R2,R3 5 1 0 -1 Zero 1 PC

  24. Empirical Summary 0000 1 0001 5 // # iterations 0010 -1 0011 5 // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Address space

  25. Empirical Summary 0000 1 0001 5 // # iterations 0010 -1 0011 5 // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 Data area Who decides data and code area? Code area

  26. Empirical Summary Your program! 0000 1 0001 5 // # iterations 0010 -1 0011 X // result 0100 LD R1 0000 0101 LD R2 0001 0110 LD R3 0010 0111 ADD R0 R0 R1 1000 ADD R2 R2 R3 1001 BRNZ 0111 1010 ST 0011 R0 int a = 1; //  R1 int n = 5; //  R2 int d = -1; //  R3 int r = 0; //  R0 while(n!=0) { // BRNZ r = r + a; // R0=R0+R1 n = n + d; // R2=R2+R3 } Data area Code area Compiler!

  27. Empirical Summary Operation code OP code Instruction code Operands Register #, address

  28. What We Need to Know …In This Class • Op code • Given n instructions  log2n bits for Opcode. That’s all? • Operands • How to represent 64b address with 32b address field?  Addressing modes! • Control flow • How to execute function calls? • Data • Data types: how to represent a floating number, e.g., 3.14159… ? • Operation Addition is enough? Subtraction, multiplication, division, AND, OR, … • Memory allocation, e.g., malloc, free, … How do they work? • (Physical) memory • How to read/write data from/to memory? • Level 1 and 2 cache, DRAM, … What are they for? How do they work? • How to integrate all to make an instruction work? • Internal structure of microprocessor, e.g., address/data/control bus, I/O, … • Advanced topics • Interrupts, pipelining, branch prediction, DMA (direct memory access), SIMD and MMX, …

  29. Class Introduction • TA • 최영근(공학2-402, cyk0521@postech.ac.kr), 이주연, 진하동, 김강민 • Grading Method • Midterm exam: 25%, Final Exam: 30%, Labs: 25%, Homework: 10%, Class Participation: 10% • Class Textbook • [Brey]: The Intel Microprocessors, 8th edition • Class Hour • 3:30pm - 4:45pm (Tuesday, Thursday) • Class website • http://cal.postech.ac.kr  Lecture  Professor Sungjoo Yoo  2011 Spring Microprocessor

  30. Class Schedule

  31. Lab Sessions • Place: LG 114 • Starts on 3/9 (Wed) • Hour • 8:00pm-9:15pm (class 1), 9:30pm-10:45pm (class 2) Wednesday • If possible, starts at 7:00pm or 7:30pm? If so, 30min intermission • Labs • Programming Exercises & Processor Applications • All lab sections will be taught during regular class hours • Lab demos will be conducted at an agreed-upon time with the TA’s • Grading • Lab Quiz 30%, Lab Report 30% (no report credit if demo is unsuccessful), Lab Demo 40%

  32. Lab Schedule

  33. Lab Grading Policy(except projects) • The full score of each lab is 10 points • Quiz (30%, 3 points): taken in the beginning of each lab • Lab Demo (40%, 4 points) • Report (30%, 3 points) • Reports should be submitted by 7:00 p.m. of the day of next lab • Penalty (per student or per team) • Being late for lab: -2 points on Lab-demo for the student • Absence without prof’s permission: The score of corresponding lab will be zero for the student • Late report submission: Report-points will be zero for the team

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