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Static Hazards

Static Hazards. Definitions. If the change of a single variable causes a momentary change in other variables, which should not occur, then a static hazard is said to exist.

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Static Hazards

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  1. Static Hazards

  2. Definitions • If the change of a single variable causes a momentary change in other variables, which should not occur, then a static hazard is said to exist. • If, after switching an input, the output has multiple transitions for a short time, then a dynamic hazard exists. For example • S/B: 0  1 • IS: 0  1  0  1 Reference: Analysis and Design of Digital Circuits and Computer Systems, Paul M. Chirlian, 1976

  3. A B A B A S B Y X1 Y X2 A B Y Y Static Hazard 2:1 Mux implemented by minimized Sum-of-Products Idealized matched delays

  4. A S B A B A B Y X1 Y X2 AND 2 A B Y Y OR 2 YS D A BUFF AND 2 A Static Hazard In real circuits, delays don't exactly match; Added delay for illustration

  5. We now have a "glitch." Static Hazard Same waveform, zoomed in.

  6. Static Hazard A B 1 1 1 0 0 1 0 0 0 1 1 0 S=0 S=1 1 0 1 0 Illustrating the minimized function on a Karnaugh map. Only two 2-input AND gates are needed for the product terms

  7. Static Hazard A B 1 1 1 0 0 1 0 0 0 1 1 0 S=0 S=1 1 0 1 0 The blue oval shows the redundant term used to cover the transition between product terms.

  8. A S B A B A B A B Y X1 Y X2 Y X3 AND 2 A B C Y Y OR 3 YS D A BUFF AND 2 A AND 2 Static Hazard How can we verify the presence and operation of the ‘redundant’ gate?

  9. Asynchronous DecodingHigh Level Used as a clock

  10. Asynchronous DecodingHigh Level - Another Form Used as a clock Decode Logic

  11. A B 1 1 1 0 0 1 00 Y Y Y Y E Q 3 E Q 2 E Q 1 E Q 0 AND 2 A B AND 2 A A B AND 2 A D 0 A B AND 2 B D 1 2:4 Decoder What happens when the inputs goes from 01 to 10?

  12. A B C A B C A B C A B C 1 1 1 0 0 1 00 Y Y Y Y E Q 3 E Q 2 E Q 1 E Q 0 AND 3 AND 3 A AND 3 A D 0 D 1 ENABLE AND 3 B 2:4 Decoder with Enable

  13. A B C D D Q DFC1B CLR D Q DFC1B CLR D Q DFC1B CLR D Q DFC1B CLR Y TCNT AND 4 CLK CLK CLK CLK CLDCK ACLR 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 0000 16 Implementation Level Terminal count of a 4-bit synchronous counter.

  14. Asynchronous DecodingGlitch Generation 01111111111111 10000000000000 … 11111111011111 11111111100000 Because of unequal propagation delays, the sequence can momentarily go through state 11111111111111 generating a glitch.

  15. Decoder Output Used As Clock From Erickson, MAPLD 2000 A5

  16. Logic Design Global Clock converted to local clock and fed to drive shift register. Asynchronous decode used as a clock. Designer unaware that a parallel asynchronous decode may glitch. Relied on back-annotated logic simulation. This construct appears repeatedly.

  17. D Q DF1 D Q DF1 D Q DF1 D Q DF1 CLK CLK CLK CLK VCC Y S1 S0 D0 D1 D2 D3 Y A Y Y GND Static HazardFlight Design Example TMR Triplet Majority Voter High-skew buffer

  18. Static HazardFlight Design Example Care is needed when using TMR circuits. First, the output of the voter may be susceptible to a logic hazard “glitch.” This is not a problem if the TMR is feeding the input of another synchronous input. However, the TMR output should never feed asynchronous inputs such as flip-flop clocks, clears, sets, read/write inputs, etc. “Design Techniques for Radiation-Hardened FPGAs” Actel Corporation, September 1997 -- based on “SEU Hardening of Field Programmable Gate Arrays (FPGAs) for Space Applications and Device Characterization,” R. Katz, R. Barto, et. al., IEEE Transactions on Nuclear Science, Dec. 1994.

  19. Dynamic Hazards We have covered static hazards. There are also dynamic hazards. An example of a dynamic hazard would be when a circuit is supposed to switch as follows: 0  1 But instead switches: 0  1  0  1 Any circuit that is static hazard free is also dynamic hazard free.

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