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Final Presentation Fast Ethernet Card with FPGA Project num. 0622 Students: Alex Shpiner

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Final Presentation Fast Ethernet Card with FPGA Project num. 0622 Students: Alex Shpiner

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  1. 21.12.03הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל המעבדה למערכות ספרתיות מהירות Final Presentation Fast Ethernet Card with FPGA Project num. 0622 Students:Alex Shpiner Eyal Azran Supervisor:Boaz Mizrahi

  2. Features • Transmitting and Receiving Ethernet frames • MAC and PHY configuration control • Driver Software for controlling card interface • Full control by the driver of the MAC features: • Full/Half Duplex • 10/100 Mb/sec • MAC address configuration • 64 bit Multicast Filter

  3. The work flow March to April 2003 VHDL studying Developing the algorithms May 2003 June to August 2003 Writing the code Sep. to Oct. 2003 Simulations Synthesis & Debug November 2003 Time line

  4. View from the top P L X FPGA M A C P H Y E T H E R N E T P C I - Data Flow - Control Signals

  5. FPGA block diagram P C I B R I D G E PHY C I F GNR MCF M A C TRN Shared bus ARB RCV

  6. CIF – CPU Interface Unit P L X CIF • Passing information (data, control signals) from PLX to all other entities. • Decode the address given from PLX and passing the data to the addressed unit.

  7. Configuration Units C I F GNR PHY MAC MCF • GNR – General Configurations • Configures MAC and PHY’s pins • MCF – MAC Configuration • Configures MAC's Internal configuration registers

  8. Transmitting and Receiving TRN C I F M A C ARB RCV • TRN – Transmitting unit • RCV – Receiving unit • The arbitration algorithm will be overviewed in the next slides

  9. Testing Units M A C PLX CIF TRN RCV PCT CIT TRT • Used during debugging • Checks the correctness of the protocols. • Filling the internal register upon signals on checked bus. • Internal registers are read through CIF. • Have addresses on memory map.

  10. The arbitration module – The Problem I want to send mail to my boyfriend!

  11. The arbitration module – The Problem I want to send mail to my boyfriend! I want to download the latest exercise in HEDVA!!

  12. The arbitration module – The Problem I want to send mail to my boyfriend! I want to download the latest exercise in HEDVA!! Problem - there is only one bus from FPGA to MAC!

  13. The arbitration module – The Solution TRN ARB RCV request request grant grant done done • Algorithm is based on Preemptive Round Robin • Differential quantum • Early finish option • RCV has higher priority

  14. Design considerations

  15. Design considerations • TRN quantum

  16. Design considerations • TRN quantum • RCV quantum

  17. Design considerations • TRN quantum • RCV quantum • TRN FIFO size

  18. Design considerations • TRN quantum • RCV quantum • TRN FIFO size • RCV FIFO size

  19. Design considerations • TRN quantum • RCV quantum • TRN FIFO size • RCV FIFO size All calculations can be found in the project book.

  20. Future versions may include… • Frame processing

  21. Future versions may include… • Frame processing Decoding

  22. Future versions may include… • Frame processing Decoding Encryption

  23. Future versions may include… • Frame processing Decoding Encryption Compression

  24. Future versions may include… • Frame processing Decoding Encryption Compression • Ping reply in hardware

  25. Future versions may include… • Frame processing Decoding Encryption Compression • Ping reply in hardware • Frames filter in hardware

  26. Future versions may include… • Frame processing Decoding Encryption Compression • Ping reply in hardware • Frames filter in hardware • And so on…

  27. Thanks… Boaz Mizrachi Eli Shoshan Michael Itzkovitz Moni Orbach Ina Rivkin Broria Zohar Anat Gavish Tomer Schatzberger Yaron Dror Gabi Zafrir Gidi Boris Kostya Dmitry And all the stuff and students of the dig lab

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