HYPER: An Interactive Synthesis Environment for Real Time Applications

1. HYPER: An Interactive Synthesis Environment for Real Time Applications Introduction to High Level Synthesis EE690 Presentation Sanjeev Gunawardena March 3rd 1998

2. Overview • Some explanation of terms • Architectures for real time applications • Introduction to the Hyper synthesis tool • Hardware Mapper for Hyper • Examples: The wavelet filter • Conclusion • Acknowledgements

3. Some Explanation of Terms • High level synthesis • A task in ASIC development which takes an algorithm, transforms it, assigns operations to suitable units and develops a schedule for the operations that share units. • Layout generators (Silicon compilers) • A tool used in ASIC development after High level synthesis that deals with the placement of hardware units and the routing of wiring between them. • Note: There is often a gap between high level synthesis and layout generators. The synthesis is considered “finished” when a design has been scheduled, but the layout tool expects a completely specified design. • Hardware Mapper • A tool that interfaces the above two steps. It derives a basic implementation of a design from a high level synthesis data representation and “decorates” the implementation with necessary details and presents a fully specified design to a layout generator.

4. Some Explanation of Terms • Hardware Mapper • Signal-flowgraph language • A language used to describe high level digital systems that have little explicit control. • Examples: Silage, Ptolemy, Comdisco, Mentor Graphics

5. Some Explanation of Terms • Control/data flowgraph FIR3 block diagram and flowgraph

6. Some Explanation of Terms • Hardware Description Language • The format in which a design is presented to a layout generator. • This is the output generated by the hardware mapper. • Examples: VHDL, SDL (the structural description language used by the Larger layout generation tools.

7. Architectures for Real Time Applications • Traditional microprocessor architecture • All operations are time-multiplexed on a single, general purpose ALU • Control driven • Hard wired (Data flow driven) architecture • Each operation is represented by a separate hardware unit • Data paths are hard wired to match the algorithmic data flow • Structures are heavily pipelined to achieve high data rates, often equaling or exceeding the maximum achievable clock rate. • Examples: Systolic arrays, speech recognition, and image processing systems. • Programmability is restricted. Results in small controller section. • Design process is very cumbersome. Requires many design iterations. • The Hyper synthesis environment can derive the data path and controller structure starting from a high-level description.

8. The HYPER System • Interactive menu-driven design environment for synthesizing high-performance digital ASICs. • Input to HYPER is a Silage description of an algorithm. • The Silage description is translated into a control/data flowgraph. • Flowgraph represents the same information as the original Silage description, but is easier to manipulate. • The flowgraph can be adorned with details not possible with the Silage description. • Example: timing, area information

9. The HYPER System The HYPER Modules

10. The HYPER System • The selection step • Assigns a unit (or group of units) from a hardware library to each type of node in the flowgraph • The library will contain many implementations of the same block each of which are optimized for performance, area, power consumption etc. • The transformation phase • Performs algorithmic transformations on the flowgraph to achieve a specific result. • Examples: • fixed-coefficient multiplications => series of adds and shifts • algebraic transformations • loop unrolling • retiming and pipelining

11. The HYPER System • The estimation stage • Provides the designer with estimated resource requirements • number of cycles in the critical path • number and type of execution units (EXUs) • number of registers associated with each EXU • number of buses connecting EXUs to registers • The assignment/scheduling step • Assigns each flowgraph node to a specific hardware unit • Derives the number of needed hardware units • NOTE: The clock period and sampling rates must be specified prior to scheduling in order to define the number of cycles available to the system.

12. The HYPER System • The hardware mapping (architecture mapping) stage • maps the flowgraph onto the selected hardware units. • Generates interconnect information • places multiplexers and buffers where needed • defines the FSM and control logic • partitions the datapath • Output of hardware mapper is a group of HDL files. • VHDL • SDL (Structural Description Language used by LargerIV silicon compiler) • After hardware mapping, the system is completely defined.

13. The Hardware Mapper (Overview) • The Hardware Mapper has two main phases • Target independent phase • extracts information from flowgraph and adds details • buffers and multiplexers added and control specifications are derived • Target specific phase • generates VHDL or SDL descriptions

14. Resources • High level synthesis tools decide how all operations of an algorithm are performed. • Involves matching a process (e.g. addition) with a pre-designed hardware unit. • The hardware units are organized in libraries. • An index lists all units and their capable operations. • A library may contain more than one unit for the same operation. • It is necessary to select the most appropriate unit (based on speed, area or power efficiency).

15. Resources • A library “data sheet” contains other relevant information for the high level synthesis tool. • Size, speed or power consumption of units • Connectivity information of units • Special unit specific information (such as multiple operation units) • The “data sheet” is the only view HYPER has of a library. It uses the “data sheet” to organize relevant information about hardware units.

16. Resources Library access routines

17. Resources Library Access Routines

18. Resources • A “technology” file is used by HYPER which describes common characteristics of units. (e.g. supply voltage). Technology File

19. Target Independent Phase • First phase of the Hardware Mapper • Translates flowgraph into an intermediate representation to allow subsequent mapping to different target platforms.

20. Target Independent Phase - Architecture Model • HYPER architecture model contains: • Execution units (EXUs) • Register files • Crossbar interconnect network

21. Target Independent Phase - Architecture Model • Register files • Have a single input port => one value written at a time • Dedicated bus exists between output of register and input of EXU it “belongs” to. • Crossbar interconnect network • provides connections from any EXU to register file. • May form different connections at different times. • Implemented by set of dedicated buses, bus drivers and MUXs. • Configured by choosing active bus drivers and selected MUX inputs.

22. HYPER’s Refined Architecture Model • Result of merging basic architecture with crossbar implementation. • A group of muxes, registers, EXUs and buffers connected only by dedicated buses is known as a “cluster”. • Typically, a cluster has only one EXU. • A cluster can have unlimited EXUs.

23. Target Independent Phase - Register Selection • Mapper considers only area when selecting register hardware. • The Mapper has four types of registers. • Register files • contain one or more registers • can be read/write or read only • can address one location for reading and one for writing in one clock cycle • all registers in the file have the same bit width (at least 1-bit) • Single registers with tri-stated outputs • can store one value at a time • read/write or read only • can be both read and written in one clock cycle • register must have a parameterizable bit width (at least 1-bit) • can be connected in parallel with other registers of this type to create a register file

24. Target Independent Phase - Register Selection • Single Registers without tri-stated outputs • can store one value at a time • read/write or read only • can both be read and written in a clock cycle • cannot be connected in parallel with other registers. • Can only be used when a HYPER design requires a register file with a single location. • Flip-flops • single-bit standard cell registers • D-FFs • rising edge triggered

25. Target Independent Phase - Register Selection Process • Determine the size of each Hyper register file, as annotated in the flowgraph. • Determine which register or combination offers a better solution • Done on a per-register-file basis • Smallest viable solution is chosen as the optimal

26. Target Independent Phase - Flowgraph Translation • Hardware mapper takes a scheduled flowgraph and extracts the necessary information from it.

27. Target Independent Phase - Bus Merging • Hardware mapper is capable of minimizing the number of physical buses in a design (optional). • Area of bus merged design is 40-60% smaller than non bus merged implementation. • Bus merging routines • Fanin bus merging • Fanout bus merging • Global bus merging Bus merging flowchart

28. Target Independent Phase - Bus Merging • Fanin bus merging • joins all input buses of a register file to a single bus • Fanout bus merging • Joins all output buses of an EXU to a single bus • Global bus merging

29. Target Independent Phase - Bus Merging Example • Seventh order IIR filter was generated by Hyper • Critical path - 10 clock cycles (16 clock cycles available time) • Implementation • 2 shifters • 1 adder • 1 subtractor • Results:

30. Target Independent Phase - Buffers and Multiplexers • After bus merging, buffers and muxes are added to the design • Buffer selection • Needed to drive large loads of buses. • Can be turned ON or OFF so that one buffer can drive a bus at a given time. • Selection routine inserts a simple buffer between EXUs and buses when the bus is driven by one EXU. • Selection routine inserts a tri-state buffers when multiple EXUs are driving the same bus.

31. Target Independent Phase - Buffers and Multiplexers • Mux selection • Always placed at the inputs of register files. • Mux servers at a bus selector for the register file with which it is associated. • Selection routines recognize how many buses are connected to the input of a register file. • Examples: • register file has one bus connected to input => no mux assigned • register file has two buses connected to input => 2:1 mux assigned

32. Target Independent Phase - Control Generation • Last step in the target independent phase of hardware mapper

33. Target Independent Phase - Control Generation • State transition graph generation (from flowgraph) • Keeps track of all the states and the operations that must take place during those states. • Determines which control signals will be used for control flow (branches, jumps etc) • Two types of control flow are supported • sequential flow (does not require any control signals to flow from the datapath to the controller) • simple loops (requires that the controller can receive feedback from the datapath to determine when or if to branch. • Example:

34. Examples - The Wavelet Filter • Contains a high pass and a low pass FIR filter. • High and low pass sections share constant coefficients for their 14 taps.

35. Examples - The Wavelet Filter • Implementation using 22 clocks/sample No bus mergingWith bus merging Buses: 15 5 Muxes : 5 4 Buffers: 18 6 Registers: 56 56 Actual layout: 7.0 mm2 4.6 mm2 Mapper predicted area: 5.2 mm2 3.6 mm2

36. Examples - The Wavelet Filter Implementation of the wavelet filter without bus merging

37. Examples - The Wavelet Filter Implementation of the wavelet filter with global bus merging

38. Examples - The Wavelet Filter (conclusion) • The mapper’s area predictions are too small because the area of control logic and control wiring is not known at the time the prediction is made. • Bus merging is clearly desirable when chip area is a concern. Fir this example, a savings of 2.4 mm2 was realized.

39. Conclusion • The Hyper synthesis environment can be effectively used to derive the data path and controller structure from a high level description (Silage) • The Hyper system is comprised of several functional blocks which include selection, transformation, estimation, assignment/scheduling and hardware mapping. • The hardware mapper takes the scheduled flowgraph generated by Hyper and maps it to specific hardware units described in a library, generating an HDL output. The hardware mapper is the interface between the high level synthesis tool (Hyper) and the silicon compiler. • The real time example shows that the design can be optimized for users specific needs (area, speed, etc)

40. Acknowledgments • The bulk of the material for this presentation was obtained from Ole Bentz’ (University of California, Berkley) masters thesis titled “A Hardware Mapper for the Hyper High Level Synthesis System.” • http://infopad.eecs.berkeley.edu/~bentz/MastersReport/index.html