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2012 EU ALSA Training P8P67 Series

2012 EU ALSA Training P8P67 Series. GRMA Brain_HUNG. P67 Platform Introduce New Feature P8P67, H67 and H61 Architecture Clock Distribution Power Flow & Critical Power P67 platform Power Sequence Cougar Point & EC Introduce Repair Notice & Trouble Shooting Guide Experience Sharing.

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2012 EU ALSA Training P8P67 Series

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  1. 2012 EU ALSA TrainingP8P67 Series GRMABrain_HUNG

  2. P67 Platform Introduce • New Feature • P8P67, H67 and H61 Architecture • Clock Distribution • Power Flow & Critical Power P67 platform • Power Sequence • Cougar Point & EC Introduce • Repair Notice & Trouble Shooting Guide • Experience Sharing

  3. P67 Platform Introduce • New Feature • P8P67, H67 and H61 Architecture • Clock Distribution • Power Flow & Critical Power P67 platform • Power Sequence • Cougar Point & EC Introduce • Repair Notice & Trouble Shooting Guide • Experience Sharing

  4. Sandy Bridge CPU Architecture • LGA 1155 • Integrated Memory Controller (IMC) • Integrated Graphics support (P67 chipset) • Dual-channel DDR3 • Intel Turbo Boost 2.0 Technology • Intel Hyper-Threading Technology (up to 4 cores, 8 threads) • PCIE Gen2 for 1x16 & 2x8 option • Intel P67/H67 Chipset Features • 2 ports SATA 6Gb/s Support • 4 ports SATA 3Gb/s Support • RAID 0, 1, 5, 10 Support • 14 ports USB2.0 • 8 Lane PCIE gen2 for x4 & x2 & x1 • No PCI support

  5. P67 Platform Introduce • New Feature • P8P67, H67 and H61 Architecture • Clock Distribution • Power Flow & Critical Power P67 platform • Power Sequence • Cougar Point & EC Introduce • Repair Notice & Trouble Shooting Guide • Experience Sharing

  6. DIGI+ VRM Load-line Calibration • Change Load-line slope • Regular, Medium, High, Ultra High, Extreme • DIGI + Current Capability • Increase over current protect point • 100%, 110%, 120%, 130%, 140% • DIGI + VRM Frequency • Change switch frequency • Auto: SSC on or off, Fix: 300MHz~500MHz with 10MHz/step DIGI+ VRM Phase Control VCORE phase number switch by different setting Standard: by CPU P-state, Optimize: load best profile, Extreme: full phase, Manual: user decide interval value

  7. GraphicalInterface & OS-likeOperation • Mouse-controlledSupport MoreSettings DisplaySystemInformation SystemPerformanceSettings BootPriority

  8. Exclusive Utility Bluetooth Module

  9. P67 Platform Introduce • New Feature • P8P67, H67 and H61 Architecture • Clock Distribution • Power Flow & Critical Power P67 platform • Power Sequence • Cougar Point & EC Introduce • Repair Notice & Trouble Shooting Guide • Experience Sharing

  10. P8P67 Series SPEC Table

  11. P67 Platform Introduce • New Feature • P8P67, H67 and H61 Architecture • Clock Distribution • Power Flow & Critical Power P67 platform • Power Sequence • Cougar Point & EC Introduce • Repair Notice & Trouble Shooting Guide • Experience Sharing

  12. P8P67 Deluxe Clock Distribution

  13. (6G SATA) +1V_CG +2.5V_DA (PCI) S_PLTRST# (PESATA)

  14. P67 Platform Introduce • New Feature • P8P67, H67 and H61 Architecture • Clock Distribution • Power Flow & Critical Power P67 platform • Power Sequence • Cougar Point & EC Introduce • Repair Notice & Trouble Shooting Guide • Experience Sharing

  15. Ex: P8P67 PRO

  16. CPU: • VCORE • Processor core power with VRM 12 design • Default voltage base on SVID • Offset mode: ±0.005~ ±0.635V, 0.005V/step • Manual mode: 0.8~1.99V, 0.005V/step • VCCIO • Processor I/O supply voltage for other than DDR3 (PCIE, DMI, Processor hot..) • Default 1.05V for Sandy Bridge processor (1.00V for future CPU) • OV range: 0.8V~1.7V, 0.00625V/step • VCCSA • Voltage for the system agent (memory controller) • Default 0.925V for Sandy Bridge processor (0.85V for future CPU) • OV range: 0.8V~1.7V, 0.00625V/step 1155 CPU LGA 1155 Socket

  17. CPU: • 1.5VDUAL • Processor I/O supply voltage for DDR3 • DRAM Device voltage • Default value is 1.5V • OV range: 1.2V~2.2V, 0.00625V/step • 1.8SFR • PLL supply voltage • Default value is 1.8V • OV range: 1.2V~2.2V, 0.00625V/step • VTTDDR • DDR3 termination voltage • Default value is 0.75V • OV range: None 1155 CPU LGA 1155 Socket

  18. PCH: • 1.05PCH: • Core power for Cougar Point • SATA, USB, DMI PLL power source • Default value is 1.05V • OV range: 0.8V~1.7V, 0.01V/step • 3VSB: • Power for suspend I/O buffers • Shut off only in G3 state (unless EuP S5) • Default value is 3.33V • 3V: • Power for core I/O buffers • Shut off in all state unless S0 • Default value is 3.33V f

  19. VCCIO: • Power to drive the processor interface signals • Default value is 1.05V (Base on CPU type) • OV range: 0.8V~1.7V, 0.00625V/step • 1.8SFR • PLL supply voltage • Default value is 1.8V • OV range: 1.2V~2.2V, 0.00625V/step f

  20. OV Method: • From EC SMBUS: • VCORE: Set SVID by EC SMBUS • From EC DAC circuit: • 1.8SFR: Set reference voltage by EC DAC output • VCCIO: Set reference voltage by EC DAC output • VCCSA: Set reference voltage by EC DAC output • 1.5VDUAL: Set reference voltage by EC DAC output • From 3933: • 1.05PCH: Sink or source current to adjust feedback voltage

  21. HW Monitor • From EC: • 1.05PCH: Detect by EC AD input • VCCIO: Detect by EC AD input • 1.8SFR: Detect by EC AD input • 1.5VDUAL: Detect by EC AD input • From SIO: • VCORE: Detect by SIO CPUVCORE input pin directly • +3V: Detect by SIO VCC input pin • +5V: Divide to 1V and detect by VIN1 input pin • +12V: Divide to 1V and detect by VIN0 input pin

  22. P67 Platform Introduce • New Feature • P8P67, H67 and H61 Architecture • Clock Distribution • Power Flow & Critical Power P67 platform • Power Sequence • Cougar Point & EC Introduce • Repair Notice & Trouble Shooting Guide • Experience Sharing

  23. Signal 1. Battery: a. RTCRST# b. S_RTCRST# Battery • 2. AC Power: • a. 5VSB_ATX, 3VSB_ATX b. 5VSB, 3VSB_ADV, 3VSB 3. RSMRST • 4. REF Voltage: • P_1.5VDUAL • P_+VCCSA • P_+VCCIO • P_1.8SFR • a. P_1.5VDUAL_REF_10 • b. P_+VCCSA_REF_10 • c. P_+VCCIO_REF_10 • d. P_1.8SFR_REF_10 SIO 3.2VCC EC RSMRST O2_ECRST#

  24. P8P67 Deluxe Power Sequence • 5. Power On: • a. O_PWRBTN#IN • b. O_PWRBTN# • 8. 12V, 5V, 3V • 9. ATX_PWRGD • 10. VCCIO, 1.5V_DUAL, VTTDDR, 1.8SFER, 1.1V, 1.05PCH • 6. SLP_S3&S4: • 7. PS_ON: SIO SIO PANEL Power Supply SIO EC

  25. P8P67 Deluxe Power Sequence • 12. S_DRAMPWRGD • 13. All Clock • 14. VCORE (initial is 1V), VCCSA • 15. P_VCORE_VRRDY_6 • 16. VRMPWRGD# • 17. SIO_PWROK • 18. O_PWROK • 11. H_VCCIOPWRGD 1156 CPU MB LogicCircuit ASP 1000C EC SIO

  26. P8P67 Deluxe Power Sequence • 19. H_CPUPWRGD • 20. H_VIDALERT#, H_VIDCLK, H_VIDDATA 1156 CPU 1156 CPU • 21. S_SPLRST • 22. O_PCIRST#_PCIEX16_1&2&3 • 23. H_CPURST# • 24. VAUX ASP 1000C

  27. P67 Platform Introduce • New Feature • P8P67, H67 and H61 Architecture • Clock Distribution • Power Flow & Critical Power P67 platform • Power Sequence • Cougar Point & EC Introduce • Repair Notice & Trouble Shooting Guide • Experience Sharing

  28. Power Interface: RTC, Power Mgmt, Misc Signals, Processor Interface Communication Interface/ Main Signals: SPI, Direct Media Interface, LPC Interface, SMBus Interface, Interrupt Interface, Clock Function Interface: PCI, USB, Serial ATA, Audio, PCI Express Interface, FAN Control

  29. RTC: S_ICH_RTCX1 S_ICH_RTCX2 input clock (the real-time clock) Connect with a 32.768 Crystal & 3V Battery Processor Interface: H_THERMTRIP Thermal Trip: When low, this signal indicates that a thermal trip from the processor occurred, and the Cougar Point will immediately transition to a S5 state H_CPUPWRGD PCH send signal for processor and processor will give the real VID to produce real VCORE for processor Misc Signal: S_INTVRMEN/ S_DSWVRMEN This signal enables the internal 1.05V regulators. It must be always pulled-up to VccRTC. RTCRST#/ SRTCRST# This signal resets the manageability register bits in the RTC well when the RTC battery is removed. INIT3_3V#

  30. 4. Power Mgmt: • SLP_S3, SLP_S4 • SLP_S3# is for power plane control. This signal shuts off power to all non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk), or S5 (Soft Off) states. • S_PDWROK • Power OK Indication for the VccDSW3_3 voltage rail. This input is tied together with RSMRST# on platforms that do not support Deep status. • DRAMPWROK • This signal should connect to the Processor’s SM_DRAMPWROK pin. The PCH asserts this pin to indicate when DRAM power is stable. • PLTRST# • Platform Reset: The Cougar Point asserts PLTRST# to reset devices on the platform (e.g., SIO, FWH, LAN, Processor, etc.) • PWRBTN#

  31. 4. Power Mgmt: • O_PWROK • PWROK can be driven asynchronously. When PWROK is negated, the cougar Point asserts PLTRST#. • O_RING# • This signal is an input from a modem. It can be enabled as a wake event, and this is preserved across power failures. • RSMRST# • Resume Well Reset: This signal is used for resetting • the resume power plane logic • VRMPWRGD • SYS_PWROK is used to inform the Cougar Point that power is stable to some other system component(s) and the system is ready to start the exit from reset. • O_RSTCON • S_SUSACK# • S_SUSWARN# • S_SLPSUS#

  32. DMI: • H_DMI_TXP[3:0] • H_DMI_TXN[3:0] • H_DMI_RXP[3:0] • H_DMI_RXN[3:0] • Direct Media Interface (DMI) is the chip-to-chip connection between the processor and Cougar Point chipset. • H_DMI_COMP • Impedance Compensation and it connects with 1.05V • 2. LPC: • F_LAD#[3:0] • F_FRAME# • F_DRQ0# • Interrupt Interface: • F_SERIRQ

  33. SPI: SPI_CS# SPI_MISO SPI Master IN Slave OUT: Data input pin for Cougar Point. SPI_MOSI SPI Master OUT Slave IN: Data output pin for Cougar Point. SPI_CLK SMBus: S_SMBDATA_PCI / S_SMBCLK_PCI Clock:

  34. 1. SATA: 2. USB: Audio: Fan Speed Control PCI Express Interface P67 Chipset support 8 PCIE USB3.0 X1 USB3.0 X1 LAN X1 PCIE Buffer X1 PCIEX16 X4

  35. +1.05PCH +BAT_3V +1.05PCH +3VSB +1.8SFR +1.05PCH +1.05PCH +3V

  36. +5V +5VSB +1.05PCH +3V +1.05ME +VCCIO +VCCIO +VCCIO 3VSB_SB

  37. Pin Straps: When booting on, some pins CPU/PCH/SIO will detect high/ low status. According these status, CPU/PCH/SIO will set different response. If strap is abnormal, it would cause CPU/PCH do the wrong action=>can’t boot up BIOS Straps: EX: P8P67 Deluxe Bit11: K_GNT_#1_PCH Bit10: N14465937 +VCCIO

  38. Power PIN: • PIN6, 18, 54, 61: +O2_3.2V_AVCC • PIN35: +3VSB • Clock PIN: • PIN9, (C_PCI_EC) • PIN58, 59 (O2_XCLI) 32.769 Crystal • Reset PIN: • PIN22 (O2_ECRST) • PIN10 (S_PLTRST#)

  39. SPI Flash : PIN56, 67, 62, 64 • MISO 56 (read control signal) • MOSI 57 (write control signal) • SPICLK 62 (clock output) • SPICS# 64 (chip select signal) • SMB Bus : PIN45, 46 • SCL0 45 (SMBUS clock) • SDA0 46 (SMBUS data) • Low Pin Count PIN:

  40. Digital-to-Analog Converter : PIN36, 38, 39, 40 • (8bit D/A converter output) • P_1.5VDUAL_REF_10 • P_VCCA_REF_10 • P_VCCIO_REF_10 • P_1.8FSR_REF_10 • Others Signals: • PIN24: O2_TP_TEST (High: normal mode using 32KHz oscillator) • PIN29: O2_DAC_SWITCH • PIN51: J_SILENT# • PIN13: SMB_SWITCH • PIN63: H_VCCIO_SEL# • (Let EC to choose this PIN to be low or high) • If VCCIO_SELis low, VCCIOmust be 1V; • If VCCIO_SELis high, VCCIOmust be 1.05V.

  41. Repair Notice & Trouble Shooting Guide • RTC/Battery • Power on • VCORE • Display/VGA/DVI • Memory • LAN/USB/other function • Experience Sharing

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