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2012 EU ALSA Training M5A99 Series

2012 EU ALSA Training M5A99 Series. GRMA Brain_HUNG. AMD 990FX / SB950 Platform Introducing New Feature M5A Series Architecture Compare with M4 Models Clock Distribution Power Flow & Critical Power Power Sequence & EUP Function Power Theory and Working Condition SB/NB Introducing

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2012 EU ALSA Training M5A99 Series

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  1. 2012 EU ALSA TrainingM5A99 Series GRMABrain_HUNG

  2. AMD 990FX / SB950 Platform Introducing • New Feature • M5A Series Architecture • Compare with M4 Models • Clock Distribution • Power Flow & Critical Power • Power Sequence & EUP Function • Power Theory and Working Condition • SB/NB Introducing • EC Introducing • Repair Experience Sharing AGENDA

  3. AMD 990FX / SB950 Platform Introducing • New Feature • M5A Series Architecture • Compare with M4 Models • Clock Distribution • Power Flow & Critical Power • Power Sequence & EUP Function • Power Theory and Working Condition • SB/NB Introducing • EC Introducing • Repair Experience Sharing AGENDA

  4. 990FX / SB950 Platform Introduce

  5. AMD 990FX / SB950 Platform Introducing • New Feature • M5A Series Architecture • Compare with M4 Models • Clock Distribution • Power Flow & Critical Power • Power Sequence & EUP Function • Power Theory and Working Condition • SB/NB Introducing • EC Introducing • Repair Experience Sharing AGENDA

  6. Implement the EFI BIOS into AMD platform. New Feature – EFI BIOS

  7. New Feature – Digi+VRM

  8. New Feature – Digi+VRM • Digi+ VRM Load-line Calibration • Change Load-line slope • Regular, Medium, High, Ultra High, Extreme • Digi+ Current Capability • Increase over current protect point • 100%, 110%, 120%, 130%, 140% • Digi+ VRM Frquency • Change switch frequency • Auto: SSC on or off, Fix: 300MHz~500MHz with 10MHz/step

  9. New Feature – Digi+VRM • Digi+ VRM Phase Control • Vcore phase number switch by different setting • Standard: by CPU P-state, Optimize: load best profile, Extreme: full phase, Manual: user decide interval value • Digi+ VRM Duty Control • Switch duty change by thermal or current • T.Probe: duty change with phase thermal balance, Extreme: duty change with phase current balance

  10. New Feature – Ai Charger in USB3.0

  11. (C5F)New Feature – CPU Level UP • HW CPU Level Up • White light is disable • Red light is enable BIOS CPU Level Up

  12. (C5F)New Feature – 4 PIN VCORE • AM3R2 8Core CPU 12V Power ~=Gulftown CPU ~= 40A (so need extra 4pin Power connector to avoid PSU protection)

  13. AMD 990FX / SB950 Platform Introducing • New Feature • M5A Series Architecture • Compare with M4 Models • Clock Distribution • Power Flow & Critical Power • Power Sequence & EUP Function • Power Theory and Working Condition • SB/NB Introducing • EC Introducing • Repair Experience Sharing AGENDA

  14. C5F Architecture

  15. M5A99X EVO Architecture Note: M5a99x EVO pciex1_1 and the back of the e-sata share with PCIE.As long as pciex1_1 card inserting, the back of e-sata can’t use.

  16. M5A97 EVO Architecture

  17. M5A Series SPEC Table

  18. AMD 990FX / SB950 Platform Introducing • New Feature • M5A Series Architecture • Compare with M4 Models • Clock Distribution • Power Flow & Critical Power • Power Sequence & EUP Function • Power Theory and Working Condition • SB/NB Introducing • EC Introducing • Repair Experience Sharing AGENDA

  19. Compare with M4 Series

  20. Compare with M4 serials. Compare with M4 Series

  21. AMD 990FX / SB950 Platform Introducing • New Feature • M5A Series Architecture • Compare with M4 Models • Clock Distribution • Power Flow & Critical Power • Power Sequence & EUP Function • Power Theory and Working Condition • SB/NB Introducing • EC Introducing • Repair Experience Sharing AGENDA

  22. ICS9LRS477 CLK Diagram X PCI EC X 1394 X X PCIEX16 PCIEX8 PCIEX4 PCIEX1 ESATA, SATA LAN USB

  23. If the SB920/950 is in external clock mode, the clock sources it requires are a 25MHz crystal as internal PLL clock source, a 32-KHz crystal for the RTC, and a 100MHz differential clock pair for the PCIe reference clocks. SB950 CLK Generation Diagram

  24. ICS9LRS477 CLK Distribution

  25. AMD 990FX / SB950 Platform Introducing • New Feature • M5A Series Architecture • Compare with M4 Models • Clock Distribution • Power Flow & Critical Power • Power Sequence & EUP Function • Power Theory and Working Condition • SB/NB Introducing • EC Introducing • Repair Experience Sharing AGENDA

  26. Critical power on SAB-990FX platform M5A99X EVO Power Flow

  27. Critical power on SAB-990FX platform • OV and H/W monitor operation. OV & HW

  28. OV & HW NO display In BIOS.

  29. Critical Power on for C5F Platform • HW Monitor • From EPF011 EC: • +VDDNB: Detect by EC AD input • +1.1VA_SB: Detect by EC AD input • From ENE3722 EC: • +VDDA2.5V: Detect by SIO CPUVCORE input pin directly • 1.5VDUAL: Detect by EC AD input • +1.2VHT: Detect by EC AD input • +1.1VNB: Detect by EC AD input • From SIO: • VCORE: Detect by SIO CPUVCORE input pin directly • +3V: Detect by SIO VCC input pin • +5V: Divide to 1V and detect by VIN1 input pin • +12V: Divide to 1V and detect by VIN0 input pin

  30. Critical Power on for C5F Platform

  31. AMD 990FX / SB950 Platform Introducing • New Feature • M5A Series Architecture • Compare with M4 Models • Clock Distribution • Power Flow & Critical Power • Power Sequence & EUP Function • Power Theory and Working Condition • SB/NB Introducing • EC Introducing • Repair Experience Sharing AGENDA

  32. SAB-990FX Power up sequence

  33. M5A Series Training Battery 1 2 +BAT_3V SR103 +BAT_3V_SB 3VSB_ATX 3VSB 3VSB SR103 ORN2 4 5 3 O2_ECRST# O2_RSMRST# SIO Power Supply O_RSMRST#

  34. 6 SIO M5A Series Training 7 Power Button O_PWRBTN# O_PWRBTN#IN SR103 8 9 SIO 7 SLP_S3# SLP_S5# O_PWRBTN# O_PSON# 9 10 DUAL POWER Power Supply MB Circuit O2_PSON# 3V, 5V, 12V SB, NB POWER Others POWER 12 SIO 11 Power Supply B_ATX_PWROK P_+VDDA2.5V_REF_10

  35. 14 M5A Series Training SIO MB Logic Circuit 13 P_+VDDA2.5V_REF_10 (Enable Signal) +VDDA2.5V HL1 H_+VDDA2.5V +3V 14 15 16 PR165 SIO VCORE IC +VDDA2.5V P_VEM_EN VCORE 18 19 VCORE IC SIO MB Logic Circuit 17 P_VRM_PG P_+1.2VHT_REF_10 +1.2VHT +1.2VHT 19 NB SIO

  36. M5A Series Training 21 20 SIO ASIC_CPUPWRGD MB Logic Circuit SB_PWRGD O_PWROK SIO 22 O_KB_RST# NB 23 S_PWRGD_NB 25 24 VCORE IC H_PWROK SVID

  37. M5A Series Training 27 SIO 26 F_LRESET# O_PCIRST#_PCIEX16_3 SIO 28 O_PCIRST#_PCIEX16_3 PCI Slot SB_PCI_RST# 29 30 H_CPURST#

  38. EUP (ERP) On/Off in S5. EUP Function Introduce

  39. M5A Power for 5VSB & EuP S5 Status

  40. Power on for EUP 0V Low High High Low Low High Turn off Low High High Low Low High High Low Low Charge High Low Low High

  41. AMD 990FX / SB950 Platform Introducing • New Feature • M5A Series Architecture • Compare with M4 Models • Clock Distribution • Power Flow & Critical Power • Power Sequence & EUP Function • Power Theory and Working Condition • SB/NB Introducing • EC Introducing • Repair Experience Sharing AGENDA

  42. Power Sequence & Distribution

  43. AM3r2 Power: VDD: VCORE VDDIO: +1.5VDUAL VDDR & VLDT: +1.2VHT VDDA: +H_VDDA2.5V VCORE Power Table

  44. +1.2VHTPower of repairing M5A Power for +1.2VHT

  45. +1.2VHTPower of repairing M5A Power for +1.2VHT

  46. +1.2VHTPower of repairing M5A Power for +1.2VHT Linear +1.5VDUAL +1.2VHT +1.2VHT isCPU HT IO BUS power 1. Check all power source. 2. Check Reference Pin level. (Controlled by EC or SIO). 3. Check Feedback Pin. (Controlled by EC or SIO). Note: 358 and 324  OP

  47. M5A Power for +VDDA2.5V Linear +3V +VDDA2.5V FROM SIO

  48. Linear M5A Power for +1.1VSB +5VSB_ATX 3VSB +1.1VSB

  49. Linear M5A Power for +1.8V 3V +1.8V REF voltage is from 3VSB through divider resistors to generate FROM SIO

  50. Linear M5A Power for +1.1VA_SB +5V +5VDUAL +1.5VDUAL +1.1VA_SB REF voltage is from 3VSB through divider resistors to generate FROM SIO

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