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Optimal Process Technology for Performance-Constrained Circuit Design

This paper discusses the determination of optimal process technology for performance-constrained circuits, specifically targeting digital signal processors and embedded devices. It outlines a comprehensive methodology involving the construction of circuits in various technologies, varying supply voltage, and measuring associated metrics such as delay, active power, and leakage power. The study emphasizes the importance of technology scaling and concludes that a 0.6µm process is suitable for low duty cycle and low frequency operations. Key related works contributing to power consumption minimization are also referenced.

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Optimal Process Technology for Performance-Constrained Circuit Design

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  1. Determining the Optimal Process Technology for Performance-Constrained Circuits Michael Boyer & Sudeep Ghosh ECE 563: Introduction to VLSI December 5th, 2006

  2. Outline • Motivation • Methodology • Related work • Results • Conclusion

  3. Performance Classes • Unconstrained • General-purpose microprocessors • Constrained • Digital signal processors • Many embedded devices • Relation to technology scaling

  4. Methodology • Build circuit in multiple technologies • Vary supply voltage and measure: • Delay • Active power • Leakage power • Vary duty cycle and frequency and compute minimum power

  5. Circuit

  6. PTM Threshold Voltages

  7. Total Power Calculation = activity factor T = circuit delay Ttarget = maximum delay = 1 / frequency

  8. Related Work • 1995: Minimizing Power Consumption in Digital CMOS Circuits • Chandrakasan & Brodersen • 2005: An Ultra Low Power System Architecture for Sensor Network Applications • Hempstead, et al

  9. Conclusion • 0.6um best choice for low duty cycle, low frequency operation • Problems: • PTMs • 1.6um

  10. References • S. Borkar, “Design Challenges of Technology Scaling”, IEEE Micro, vol. 19, no. 4, pp. 23-29, 1999. • A. Chandrakasan and R. Brodersen, “Minimizing Power Consumption in Digital CMOS Circuits”, Proceedings of the IEEE, vol. 83, no. 4, pp. 498-523, 1995. • M. Hempstead, et al, “An Ultra Low Power System Architecture for Sensor Network Applications”, Proceedings of the 32nd International Symposium on Computer Architecture, 2005. • Y. Cao, et al, “New Paradigm of Predictive MOSFET and Interconnect Modeling for Early Circuit Simulation”, CICC, pp. 201-204, 2000. • C. Hu, “BSIM Model for Circuit Design Using Advanced Technologies”, Symp. VLSI Circuits, pp. 5-6, 2001.

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