The Applications of Nano Materials

1. The Applications of Nano Materials Department of Chemical and Materials Engineering San Jose State University Zhen Guo, Ph. D.

2. How to study Nanomaterials Part I -- Done Basic Materials Science Principles Microstructure Materials Properties Applications Processing Part II – Done Part III – This one

3. The Applications of Nano Materials Electronics Magnetic Device Structure Nano Materials Applications Daily Life consumable Optics Renewable Energy MEMS Bio Device

4. Applications of Nano Materials

5. Session X – Nano Electric Materials -- Single Electron Transistor -- Other Novel Transistor -- Nano Crystal Memory -- Phase Change Memory

6. MOSFET Principles • Review MOSFET principles – accumulations, depletion, and inversion. Vt, Vg, Ids, Idsat, etc. • Just remember that Electrons are like water, source / drain like two bottles, channel is a pipe in between and gate is like a valve to open / close the pipe...

7. Single Electron Box • Single Electron Box • One Quantum Dot • Two Electrodes • Tunneling Junction • Control Gate Capacitor • Electrons are injected/ejected into / from quantum dots thru tunneling junctions. • Extra electrons injected into quantum dots will lead to excessive charging energy Courtesy from Rainer Waser: Nano-electronics and Information technology PP427-445

8. Coulomb Blockade • Coulomb Blockade is caused by excessive charging energy Wc which increase as the size of quantum dot decrease With adding extra electron into QD r => Csp => Wc Wc=e2/2Csp When Wc >> kT, thermal energy is no longer sufficient to overcome excessive charging energy => Coulomb Blockade • Quantum Effect of Coulomb Blockade – Quantum confinement cause energy level split => next electrons may need to occupy higher energy level Wc = e2/2Csp + DE (n) http://www.plus2physics.com/capacitors/study_material.asp

9. Bias Condition for Coulomb Blockade • When gate voltage is zero, the charge at quantum dot is zero. • As gate voltage increases to a certain value, electrons are attracted to quantum dot, making 1e net charge of dot • Further increase gate voltage will increase electron number.

10. Bias Condition for Coulomb Blockade • To maintain the electron number in quantum dots, we have • To substitute the equations in previous slide, we obtained When Consider both sides, we have or Courtesy from Rainer Waser: Nano-electronics and Information technology

11. Single Electron Transistor (SET) • SET – three terminal switching devicethat can transfer electron one by one from source to drain -- can be considered as two independent tunneling junctions -- Each will have to satisfy Coulomb Blockade conditions Courtesy from Rainer Waser: Nano-electronics and Information technology

12. Single Electron Transistor (SET) Con’d: Two Equations can be reduced to Source Blue Line Drain Red Line • In grey area, both source and drain satisfy coulomb blockade condition for same n value=>Fixed # electrons. • In green area, source and drain satisfy different value. • -- In Area A, for source junction, it satisfy n=1 so one electron will tunnel from source to QD • -- Once electron at QD, it found that drain junction is favor n=0 so this electron will further tunnel to drain • -- Current Flow from source to drain • -- Giving a small Vds, Ids will vary with Vg periodically • -- Vg can behave as a switch. Vg=0, need Vds greater than threshold, Vg=e/2Cg, linear Ids verse Vds

13. Fabrication of SET (I) • PADOX – Pattern Dependent Oxidization • -- 1-D Si Nano Wire connected with 2-D Si layers at both ends • -- Oxidization process forms tunneling barriers at both ends. • -- Can be either width or thickness modulated. • -- For Vertical PADOX, it is possible to form 2 tiny islands

14. Fabrication of SET (II) • Surface-Treated SOI Channel • -- 1-D SOI channel intentionally undulated with alkaline based solutions • -- The nano scaled undulation results in potential fluctuation due to the difference of quantum confinement effect from one part to another. • -- The channel effectively splits into several quantum dots. • -- Process is completely compatible with current CMOS fabrications

15. Advantage and Disadvantages • Advantages: • Lower power assumption • Good scalability • Disadvantages • Operated usually at low temperature • High output impedance due to tunneling • Vds has to be less than Vg to have gate fully control the switch.

16. Other Novel Logic Transistor -- On state: for positive gate voltage, the polarization vector P is directed towards Channel. -- Cohesive voltage Vc keep remanent polarization Pr large enough to invert channel and keep current flow even when Vg=0 (non-volatile operation) -- Off State: negative gate voltage will bring Pr direct opposite to channel and + charge are accumulated in the channel region. Channel resistance is high and no current flow • Ferro-Electric Field Effect Transistor (FeFET) Courtesy from Rainer Waser: Nano-electronics and Information technology

17. Other Novel Logic Transistor • Spintronic transistor – based on the effect of spin orientation on electron’s transportation properties -- Source and drain are both ferro-magnetic materials with identical magnetization direction -- Channel is a hetero-junction of semiconductor compound with a highly mobile 2-D electron gas. -- Source will inject a spin-polarized current into channel. Without gate voltage, spin will remain unchanged so electron travel to drain on a very high velocity (1% of speed of light) -- When applied gate voltage, spin direction will be rotated by magnetic field so the spin is no longer aligned with drain side => More scattering, higher resistance, lower velocity.

18. Other Novel Logic Transistor • Molecular transistor – Single Molecular acting as electronic switch and storage elements

19. Traditional Floating Gate Memory Nano Crystal Flash Memory Floating Gate Usually Poly Si Nano Crystal Memory • Introduction • Why Nano Crystal Memory • New Development on Nano Crystal Memory

21. Recent Trend in Non-volatile Memory • Current flash memory is continuing to follow Moore’s Law at 90 / 65 / 45nm Nodes • -- 18 years for 9 generations • ETOX and NAND will still be the mainstream flash memory in next 5 years. • There is no clear roadmap to continuously scale flash memory beyond 32nm node.

22. ITRS Roadmap for Emerging Memory Device (2003) 63

23. Nano-crystal Memory for Technology Gap S. J. Baik et al, IDEM, 2003

24. Traditional Floating Gate Memory Nano Crystal Flash Memory Floating Gate Usually Poly Si Principle of Nano Crystal Memory Improvement of Data Retention and SILT.

25. Nano Crystal as Storing Bit • Nano Crystal Technology has been studied extensively to replace traditional floating gate as charge storage media. • Advantages: • Scalability with Channel Tunneling and Erase • Compatible with Traditional CMOS Platform • Improved Charge Retention and Endurance • Potential Multi Bit usage • Challenges: • Strictly control the size and distribution of nano crystals • Still Litho node limited • Much work to be done for a integrated reliable and high yield process

26. Silicon Nano Crystal as Storing Media • Reduce SILC and thus improve data retention and endurance • Decrease gate coupling and thus improve leakage and erase saturation • Possible multi-bit storage as particle size goes down to discrete energy state of electrons R. Muralidhar et al. IDEM, 2003

27. Metal Dots as Storage Media C. Lee, et al, IDEM, 2003 • Metal dots can be Co, W or Au • Suppose to be better than Si as work function is higher (more attractive to electrons) • Multilayer can improve retention and endurance M. Takata, et al, IDEM, 2003

28. Silicon Nano Crystals Produced by CVD Methods (I) • A Si-rich SiOx thin film is deposited on Si surface by PECVD method. The non-stoichemetry are controlled by gas flow ratios. • An furnace annealing were performed on this film at 1000C in N2 atmosphere to precipitate Si Nano crystals out of supersaturated film. -- U.S. Pattern Pending

29. Si – SiO2 Binary Phase Diagram -- Si has no solubility in SiO2 at equilibrium state

30. Silicon Nano Crystals Produced by CVD Methods (II) • Thermal Decomposition of SiH4 precursor on Silicon surface for Si Nano crystals . • No Anneal Step is required. • Most compatible with current CMOS technology. • Challenge is how to control location and size distribution. -- U.S. Pattern Pending

31. Other Ideas of Synthesis Nano Crystals • Controllable Nucleation and Growth • Volmer-Weber Growth (3-D Island Growth) on Thin Film • In-Situ Phase Segregation (Spinodal Decomposition) • Pre-patterned Growth (Polymer Precursor Self-assembly)

32. Summary • Nano storing bit can and must meet Si technology in 5 years. • Nano crystal memory is the most promising one to be compatible with CMOS platform • Many challenges still exist ranging from manufacturing nano particles to integration into traditional process flow • Materials scientist can definitely help!

33. Phase Transformation Memory Phase Transformation Memory • Same principle as DVD • Using transformation between amorphous and crystalline phase based on cooling speed. • Different phases has different optical and electrical properties. • Easy to be integrated and scalable.

34. Stephen Lai, Intel, December 2003.

35. Basic Architecture of Nano Crystal Memory R. Muralidhar et al. IDEM, 2003 S. Tiwari et al. Appl, Phy lett, 1996 Floating nano crystals can be -- Silicon nano crystals (multiple or single) -- Silicon nano wires -- Metal nano dots (single or Multi layers)

36. Nucleation and Growth Control • Nano particles need strong nucleation and slow growth • Low temperature (high DT) promote nucleation and slow down growth • The distance among nucleation sites has to be bigger than diffusion length • Nucleus size should be controlled around critical radius

37. Volmer-Weber Growth • 3-D island growth • Neither complete wetting nor complete non-wetting surface • Island size and distribution controlled by heterogeneous nucleation sites

38. Spontaneous transformation due to instability No nucleation barriers-only require local compositional fluctuations Wave length (or particle size) is a function of undercooling Misfit strain will also play a key role in particle size (barriers for growth) Spinodal Decomposition

39. Self-Assembly Patterning K. W. Guarini et. al. IDEM, 2003