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Unit 9

Unit 9. Multiplexers, Decoders, and Programmable Logic Devices. Outlines. 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices (PLD) Programmable Logic Arrays (PLA) Programmable Array Logic (PAL)

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Unit 9

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  1. Unit 9 Multiplexers, Decoders, and Programmable Logic Devices

  2. Outlines • 9.1 Introduction • 9.2 Multiplexers • 9.3 Three-State Buffers • 9.4 Decoders and Encoders • 9.5 Read-Only Memories • 9.6 Programmable Logic Devices (PLD) Programmable Logic Arrays (PLA) Programmable Array Logic (PAL) • 9.7 Complex Programmable Logic Devices (CPLD) • 9.8 Field Programmable Gate Arrays (FPGA) Unit 09

  3. Integrated Circuits (1/2) • Integrated Circuits (IC) are classified by # of gates • Small-scale integration (SSI) • NAND, NOR, AND, OR, inverter, Flip-Flop • 1-4 gates, 6 inverters, 1-2 Flip-flops • Medium-scale integration (MSI) • Adder, multiplexer, decoder, register, counter • 12-100 gates • Large-scale integration (LSI) • Memories, microprocessors • 100- a few thousand gates Unit 09

  4. Integrated Circuits (2/2) • Integrated Circuits (IC) are classified by # of gates • Very-large-scale integration (VLSI) • Microprocessors, FPGA, Application-specific integrated circuit (ASIC),… • Several thousand gates or more • Ultra Large-scale integration (ULSI) • Memories, microprocessors • More than 109 transistors • The cost of wiring, designing and maintaining of digital system is lower when LSI and VLSI functions are used. Unit 09

  5. Topics • 9.1 Introduction • 9.2 Multiplexers • 9.3 Three-State Buffers • 9.4 Decoders and Encoders • 9.5 Read-Only Memories • 9.6 Programmable Logic Devices (PLD) Programmable Logic Arrays (PLA) Programmable Array Logic (PAL) • 9.7 Complex Programmable Logic Devices (CPLD) • 9.8 Field Programmable Gate Arrays (FPGA) Unit 09

  6. Multiplexers (1/4) • Multiplexers (MUX, or data selector) • A MUX has a group of data inputs and a group of control inputs. • The control inputs are used to select one of the data inputs and connect it to the output terminal. • 2-to-1 MUX • A=0, Z=I0 • A=1, Z=I1 • Z=A’I0+AI1 Unit 09

  7. Multiplexers (2/4) • 4-to-1, 8-to-1, 2n-to-1 MUX • Logic equation for 8-to-1 MUX Unit 09

  8. Multiplexers (3/4) • Logic Diagram for 8-to-1 MUX Unit 09

  9. Multiplexers (4/4) • Logic equation for 2n-to-1 MUX where is a minterm of the n control variables and is the corresponding data input Unit 09

  10. DE-MUltipleXer (DEMUX) • DEMUX takes a single input and direct it to one of several outputs. DEMUX S0 S1 P0 P1 P2 P3 P0 P1 P2 P3 0 0 A 0 0 0 0 1 0 A 0 0 1 0 0 0 A 0 1 1 0 0 0 A A S0 S1 Unit 09

  11. Usage of Multiplexers (1/3) • Quad Multiplexer Used to Select Data A=0, (z0z1z2z3)=(x0x1x2x3) A=1, (z0z1z2z3)=(y0y1y2y3) Unit 09

  12. Usage of Multiplexers (2/3) • Figure 18-13 in page 550 -- Block diagram for binary divider Unit 09

  13. Usage of Multiplexers (3/3) • Use a 4-to-1 MUX to be an XOR gate • Use an 8-to-1 MUX to generate f(a,b,c)=Σm(1,3,4,7) • Use an 8-to-1 MUX to generate f(a,b,c,d)=Σm(0,1,3,6,7,8,11,12,14) • Multiplexed Transmission System Unit 09

  14. Topics • 9.1 Introduction • 9.2 Multiplexers • 9.3 Three-State Buffers • 9.4 Decoders and Encoders • 9.5 Read-Only Memories • 9.6 Programmable Logic Devices (PLD) Programmable Logic Arrays (PLA) Programmable Array Logic (PAL) • 9.7 Complex Programmable Logic Devices (CPLD) • 9.8 Field Programmable Gate Arrays (FPGA) Unit 09

  15. Three-State Buffers (1/5) • A gate output can only be connected to a limited number of other device inputs without degrading the performance of a digital system. • A buffer may be used to increase the driving capability of a gate output. Unit 09

  16. Three-State Buffers (2/5) • Three-state buffer (Tri-state buffer) • B=1, C=A. (C=0 or 1) • B=0, C=Z. • C acts like anopen circuit. • C is effectivelydisconnected from the buffer outputso that no current can flow. • This is referred to a Hi-Z (high-impedance) state of the output because the circuit offers a very high resistance or impedance to the flow of current. Unit 09

  17. Three-State Buffers (3/5) • Four kinds of Three-State Buffers Unit 09

  18. Three-State Buffers (4/5) • Data Selection Using Three-State Buffers D=B’A+BC Unit 09

  19. Three-State Buffers (5/5) • Circuit with Two Three-State Buffers Unit 09

  20. Usage of Three-State Buffers (1/2) • 4-Bit Adder with four sources for one operand • Use a 4-to-1 MUX to select one of several sources • Set up a three-state bus: A bus is driven by three-state buffers Unit 09

  21. Usage of Three-State Buffers (2/2) • Bi-directional I/O Pin • Buffer is enabled, Output pin • Buffer is disabled, Input pin Unit 09

  22. Topics • 9.1 Introduction • 9.2 Multiplexers • 9.3 Three-State Buffers • 9.4 Decoders and Encoders • 9.5 Read-Only Memories • 9.6 Programmable Logic Devices (PLD) Programmable Logic Arrays (PLA) Programmable Array Logic (PAL) • 9.7 Complex Programmable Logic Devices (CPLD) • 9.8 Field Programmable Gate Arrays (FPGA) Unit 09

  23. Decoders • To generates all of minterms: yi=mi • 3-to-8 Decoder: Unit 09

  24. 4-to-10 Line Decoder (1/2) • 4-to-10 Line Decoder with Inverted Output yi=mi’=Mi Unit 09

  25. 4-to-10 Line Decoder (2/2) Unit 09

  26. Usage of Line Decoder • Realize the following functions using a decoder. Unit 09

  27. Encoders • The inverse function of a decoder • 8-to-3 Priority Encoder Unit 09

  28. Topics • 9.1 Introduction • 9.2 Multiplexers • 9.3 Three-State Buffers • 9.4 Decoders and Encoders • 9.5 Read-Only Memories • 9.6 Programmable Logic Devices (PLD) Programmable Logic Arrays (PLA) Programmable Array Logic (PAL) • 9.7 Complex Programmable Logic Devices (CPLD) • 9.8 Field Programmable Gate Arrays (FPGA) Unit 09

  29. Read-Only Memories (1/3) • Consists of semiconductor devices that interconnected to store binary data Unit 09

  30. Read-Only Memories (2/3) • A ROM consists of a decoder and a memory array. • The basic architecture of ROM Unit 09

  31. Read-Only Memories (3-1/3) 1 0 0 0 A=0 B=0 C=0 0 0 0 0 A=B=C=0: F=1010 A=B=C=1: F=0101 1 0 1 0 Unit 09

  32. Read-Only Memories (3-2/3) 0 0 0 0 A=1 B=1 C=1 0 0 0 1 A=B=C=0: F=1010 A=B=C=1: F=0101 0 1 0 1 Unit 09

  33. Usage of ROM (1/4) • A ROM can realize m functions (F1,F2,…Fn) of n variables. • Multiple-output combinational circuits can be realized using ROMs. • Realize the following functions using ROM. Unit 09

  34. Usage of ROM (2/4) Unit 09

  35. Usage of ROM (3/4) • Design a code converter that converts a 4-bit binary number to a hexadecimal digit and outputs the 7-bit ASCII code. Unit 09

  36. Usage of ROM (4/4) • Because , the ROM needs only five outputs. The ROM size is 16 words by 5 bits. The decoder is a 4-to-16 decoder. Unit 09

  37. Type of ROMs • Mask-programmable ROMs • Programmable ROMs (PROMs) • Electrically Erasable Programmable ROMs (EEPROMs, E2PROMs) • Flash memories Flash memory has built-in programming and erase capability so that data can be written to it while it is in place in a circuit without the need for a separate programmer. Unit 09

  38. Topics • 9.1 Introduction • 9.2 Multiplexers • 9.3 Three-State Buffers • 9.4 Decoders and Encoders • 9.5 Read-Only Memories • 9.6 Programmable Logic Devices (PLD) Programmable Logic Arrays (PLA) Programmable Array Logic (PAL) • 9.7 Complex Programmable Logic Devices (CPLD) • 9.8 Field Programmable Gate Arrays (FPGA) Unit 09

  39. Programmable Logic Devices • Programmable Logic Device (PLD) is a general name for a digital integrated circuit capable of being programmed to provide a variety of different logic functions. • Lower cost • Design a larger circuit • Changing the programming of PLD • Without having to change the wiring • Programmable logic arrays (PLAs) • Programmable array Logic devices (PALs) • Complex programmable logic devices (CPLDs) • Field-programmable gate arrays (FPGAs) Unit 09

  40. PLA • Perform the same basic function as a ROM • A PLA with n inputs and m outputs can realize k products of n variables then generate m functions . Unit 09

  41. Example 1 of PLA (1/4) • Realize the following functions using PLA. • Using a PLA with 4 inputs, 4 outputs and 5 internal product terms. AND Array Ex: A=1, B=0, C=1  m5=1  AC=1, others =0 F0=F1=F2=0, F3=1 Unit 09

  42. Example 1 of PLA (2/4) • Construct the PLAtable. Unit 09

  43. Example 1 of PLA (3/4) • AND-ORequivalent circuit Unit 09

  44. Example 1 of PLA (4-14) AND Array OR Array Unit 09

  45. Example 1 of PLA (4-2/4) 1 0 0 1 1 0 0 0 0 0 1 0 0 0 1 Unit 09

  46. Example 2 of PLA (1/2) • Use PLA to realize f1,f2, and f3. Using a PLA with 4 inputs, 3 outputs and 6 internal product terms. • Construct the PLAtable Unit 09

  47. Example 2 of PLA (2/2) Unit 09

  48. PAL (1/2) • A special case of the PLA in which the AND array is programmable and the OR array is fixed. • Less expensive than the more general PLA • Easier to program Unit 09

  49. PAL (2/2) Unit 09

  50. Example of PAL • Implement a full adder using a PAL. Unit 09

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